Errata
28
Specification Update
AA35.
The IA32_MC0_STATUS and IA32_MC1_STATUS Overflow Bit is not
set when Multiple Un-correctable Machine Check Errors Occur at the
Same Time
Problem:
When two enabled MC0/MC1 un-correctable machine check errors are
detected in the same bank in the same internal clock cycle, the highest
priority error will be logged in IA32_MC0_STATUS / IA32_MC1_STATUS
register, but the overflow bit may not be set.
Implication:
The highest priority error will be logged and signaled if enabled, but the
overflow bit in the IA32_MC0_STATUS/ IA32_MC1_STATUS register may not
be set.
Workaround:
None identified.
Status:
For the steppings affected, see the
Summary Tables of Changes.
AA36.
IRET under Certain Conditions May Cause an Unexpected Alignment
Check Exception
Problem:
In IA-32e mode, it is possible to get an Alignment Check Exception (#AC) on
the IRET instruction even though alignment checks were disabled at the start
of the IRET. This can only occur if the IRET instruction is returning from CPL3
code to CPL3 code. IRETs from CPL0/1/2 are not affected. This erratum can
occur if the EFLAGS value on the stack has the AC flag set, and the interrupt
handler's stack is misaligned. In IA-32e mode, RSP is aligned to a 16-byte
boundary before pushing the stack frame.
Implication:
In IA-32e mode, under the conditions given above, an IRET can get a #AC
even if alignment checks are disabled at the start of the IRET. This erratum
can only be observed with a software generated stack frame.
Workaround:
Software should not generate misaligned stack frames for use with IRET.
Status:
For the steppings affected, see the
Summary Tables of Changes.
AA37.
Processor May Fault When the Upper 8 Bytes of Segment Selector Is
Loaded from a Far Jump through a Call Gate via the Local Descriptor
Table
Problem:
In IA-32e mode of the Intel EM64T processor, control transfers through a call
gate via the Local Descriptor Table (LDT) that uses a 16-byte descriptor, the
upper 8-byte access may wrap and access an incorrect descriptor in the LDT.
This only occurs on an LDT with a LIMIT>0x10008 with a 16-byte descriptor
that has a selector of 0xFFFC.
Implication:
In the event this erratum occurs, the upper 8-byte access may wrap and
access an incorrect descriptor within the LDT, potentially resulting in a fault
or system hang. Intel has not observed this erratum with any commercially
available software.
Workaround:
None identified.
Status:
For the steppings affected, see the
Summary Tables of Changes
.
