Errata
18
Specification Update
AA6.
FXRSTOR May Not Restore Non-canonical Effective Addresses on
Processors with Intel
®
Extended Memory 64 Technology (Intel
®
EM64T) Enabled
Problem:
If an x87 data instruction has been executed with a non-canonical effective
address, FXSAVE may store that non-canonical FP Data Pointer (FDP) value
into the save image. An FXRSTOR instruction executed with 64-bit operand
size may signal a General Protection Fault (#GP) if the FDP or FP Instruction
Pointer (FIP) is in non-canonical form.
Implication:
When this erratum occurs, Intel EM64T enabled systems may encounter an
unintended #GP fault.
Workaround:
Software should avoid using non-canonical effective addressing in EM64T
enabled processors. BIOS can contain a workaround for this
erratum removing the unintended #GP fault on FXRSTOR.
Status:
For the steppings affected, see the
Summary Tables of Changes
.
AA7.
A Push of ESP That Faults May Zero the Upper 32 Bits of RSP
Problem:
In the event that a push ESP instruction, that faults, is executed in
compatibility mode, the processor will incorrectly zero upper 32-bits of RSP.
Implication:
A Push of ESP in compatibility mode will zero the upper 32-bits of RSP. Due
to this erratum, this instruction fault may change the contents of RSP. This
erratum has not been observed in commercially available software.
Workaround:
None identified.
Status:
For the steppings affected, see the
Summary Tables of Changes
.
AA8.
Checking of Page Table Base Address May Not Match the Address Bit
Width Supported by the Platform
Problem:
If the page table base address, included in the page map level-4 table, page-
directory pointer table, page-directory table or page table, exceeds the
physical address range supported by the platform (e.g. 36-bit) and it is less
than the implemented address range (e.g. 40-bit), the processor does not
check if the address is invalid.
Implication:
If software sets such invalid physical address in those tables, the processor
does not generate a page fault (#PF) upon access to that virtual address, and
the access results in an incorrect read or write. If BIOS provides only valid
physical address ranges to the operating system, this erratum will not occur.
Workaround:
BIOS must provide valid physical address ranges to the operating system.
Status:
For the steppings affected, see the
Summary Tables of Changes
.
