IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -13
Q201: D788E001BRFP266/D708E001BRFP266 (Audio DSP)
DTR-5.8
System Diagram
Device Block Diagram
BLOCK DIAGRAM
Program/Data
RAM
256K Bytes
256
256
Program/Data
ROM Page1
256K Bytes
256
256
256K Bytes
ROM Page3
Program/Data
Program/Data
ROM Page2
256K Bytes
32
32
DMP
PMP
CSP
32
256
Program
Cache
32K Bytes
64
D1
Data
R/W
R/W
Data
D2
64
256
Program
Fetch
INT
I/O
C67x+ CPU
Memory
Controller
32
High-Performance
Crossbar Switch
32
McASP DMA Bus
JTAG EMU
32
32
32
32
32
32
32
Peripheral Configuration Bus
EMIF
32
Events
In
32
MAX1
MAX0
32
CONTROL
32
Interrupts
Out
I/O
dMAX
McASP0
16 Serializers
McASP1
6 Serializers
McASP2
2 Serializers
DIT Only
SPI1
SPI0
I2C1
I2C0
RTI
32
PLL
Peripheral Interrupt and DMA Events
32
32
32
32
256K
Bytes
RAM
Bytes
ROM
768K
Memory Controller
dMAX
McASP0
SPI1
McASP1
I2C0
I2C1
RTI
SPIO
McASP2
PLL
OSC
ASYNC
FLASH
100-MHz/
133-MHz
SDRAM
DSP
Host
Microprocessor
Audio Zone 1
SPI or I2C
Control (optional)
Audio Zone 2
Audio Zone 3
CODEC, DIR,
ADC, DAC, DSD,
Network
Network
ADC, DAC, DSD,
CODEC, DIR,
Digital Out
DSP Control
SPI or I2C
5 Independent Audio
Zones (3 TX + 2 RX)
16 Serial Data Pins
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TEL 13942296513
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