IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -20
Q282: ES29LV160ET-70TG (16 Mbit Flash Memory)
DTR-5.8
BLOCK DIAGRAM
Command
Register
Analog Bias
Generator
Address Latch
BYTE#
CE#
OE#
A<0:19>
RESET#
Vcc
Vss
Chip Enable
Output Enable
Logic
Vcc Detector
Timer/
Counter
Y-Decoder
X-Decoder
Y-Decoder
Cell Array
Data Latch/
Sense Amps
Input/Output
Buffers
Sector Switches
DQ0-DQ15(A-1)
RY/BY#
Write
State
Machine
WE
#
NC
NC
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
A16
BYTE#
Vss
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
Vcc
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
Vss
CE#
A0
4
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
48-Pin Standard TSOP
ES29LV160
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TEL 13942296513
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