Copyright Innovative Technology Ltd 2008 GA333-5
NOTES:
•
All outputs are open collector transistors.
•
All Inputs are held high to in5V via 10K
Ω
. The input structure is a
CMOS gate with anti-static protection fitted.
Interface logic levels
Logic low
Logic high
Inputs
0V <low<0.5V
3.7 V <high<12V
Outputs with 2K2
Ω
pull up 0.6V
Pull up voltage of host interface
Maximum Current Sink
50mA per output
Table 6
- Interface Logic Levels
5.3 SERIAL INTERFACE INPUT AND OUTPUTS
CAUTION: THE SERIAL INTERFACES WILL ONLY WORK IF THE RELEVANT INTERFACE
SOFTWARE IS CORRECTLY INSTALLED.
Name
Description
SSP TxD
Vend 1
SSP RxD
Inhibit 1
Table 7
- Serial Interface Inputs and Outputs
NV10 Operations Manual
11
Содержание NV10
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