Infineon TriBoard TC3 6 Series, Руководство пользователя

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User Manual 7-3 V1.0
TriBoard TC3X6 TH V1.0 and TriBoard TC3X6 V1.0 2019-09
TriBoard Manual TC3X6
Hardware: TriBoard TC3X6 TH V1.0 and TriBoard TC3X6 V1.0
Schematic and Layout
Figure 7-2 Schematic -
Clock, Config, Debug, Ports and ADC
1 1
2 2
3 3
4 4
5 5
6 6
7 7
8 8
D
D
C
C
B
B
A
A
2
Infineon Technologies AG
A
T
V
M
C
ACE ATV CES
Am Campeon 1-12 D-85579 Neubiberg T
el.: +49-89-234-0
7
23.04.2019
Number: Date: Sheet:
of
TriBoard TC3X6 Clock, Config, Debug, Ports, ADC
1.0
Revision:
G
:\
Technic
a
l_Support
\Tri
C
ore
\T
ri
B
oard
\E
D
A
_
D
X
P
\Tri
B
oard AU
R
IX
2
G
\T
ri
B
oard
T
C
3
X
6
\T
ri
B
oard
T
C
3
X
6 V1.X\
C
lk_Cf
g
_
D
bg_Port
s_
A
dc.sch
F
ile:
P21 .6
PORT[00..34]
CLOCK & TE
S
T
M
ODE
XTAL1
L1
4
XTAL2
L1
3
T
RST
K12
T
CK / DAP0
G14
P21.6 / TDI
F13
P21.7 / TDO / DAP2
F14
T
M
S / DAP1
G11
P20.2 / TE
S
T
M
ODE
G13
JT
AG / DAP / OCDS1
VDD
M1
3
VEXT
M1
4
VSS
K14
U201B T
C3X6
P15.3 / SCLK2
A10
P15.5 / SDA0
D10
P20.14
B14
P11.6 / TXEN
C6
P11.9 / RXD1A
A5
P11.3 / TXD0
B6
P14.1 / ARX0A
B10
P14.0 / ATX0
A9
P15.1 / ARX1A
A12
P15.0 / ATX1
A13
P20.11
D14
P20.12
D13
P20.13
C13
P20.8 / CAN00_TXD
F12
VFLE
X
D5
P11.12 / REFCLKA
A4
P11.10 / RXD0A
B5
P11.2 / TXD1
A6
P15.4 / SCL
B11
P33.5
N9
P20.7 / CAN00_RXDB
E1
2
P11.11 / RXDVA
C5
ON BOARD USED PERIPHERALS / PINS
P14.5 / HWCFG1
B9
P14.6 / SLSO22
C9
P15.7 / MRST2
B
D8
P15.6 / MT
SR2
A11
P33.7
L1
0
P33.4
L8
P33.6
P9
ASCLIN
CAN
QSPI / TL
F35584
E
RAY I2C
LED
s
P14.4 / HWCFG6
C10
P14.2 / HWCFG2
D9
P33.8 / SMU_FSP0
L9
P33.9
P10
P21.3 / RXD0P
J1
4
P21.4 / TXD0N
J1
3
P21.5 / TXD0P
H14
P14.3 / HWCFG3
C11
P10.5 / HWCFG4
F4
P10.6 / HWCFG5
E4
P20.0 / SYSCLK
H13
P21.2 / RXD0N
K13
HSCT
HWCFG
P33.10
N11
P33.11
N10
E
T
HERNET
BUTT
ON
P20.10
C14
P20.9 / REQ7_0
D12
E
RAY
P02.0 / TXD0A
B1
P02.1 / RXD0A2
C1
P02.2 / TXD0B
C2
P02.3 / RXD0B2
D3
P02.4 / TXEN0A
D2
P02.5 / TXEN
0
B
D1
P10.2 / REQ2_0
A3
P10.1
B3
P00.0 / MDIOA
G4
P02.8 / MD
C
E3
P10.3 / REQ3_0
A2
P00.4 / CAN11_TXD
F1
P00.5 / CAN11_RXDB
H3
P02.7
E2
U201C T
C3X6
PORT[00..34]
P20 .2
P21.7
GND
R206 opt
XTAL[1..2]
XTAL1 XTAL2
R203 50R_opt
VSSOSC
D
E
BUG..
R207 0R
C202 10pF
C201 10pF
VSSOSC
VSSOSC
1 2
Y201 20MH
z
R201 10K
V_UC
P20.2
R202 opt
GND
XTAL[1..2]
R204 0R R205 0R
R216 0R
DAP 2
R209 0R
R208 0R
VDD
VSSOSC
V_UC
VSSOSC
VDDOSC
VEXTO
S
C
AN[0..39]
V_VR
GND
VDDM
+
3V3
F
OR 5V ADC
F
OR 3,3V ADC
AN0 / EDS3PA
L7
AN1 / EDS3NA
P6
AN2 / EDS0PA
L6
AN3 / EDS0NA
M6
E
VADC / EDSADC
AN4
N6
AN5
L5
AN6
M5
AN32 / P40.4
K1
AN7
P5
AN8
N5
AN10
M4
AN11
N4
AN12 / EDS0PB
M3
AN13 / EDS0NB
N2
AN16 (NC)
M1
AN17 (NC)
M2
AN24 / EDS2PB / P40.0 (NC)
L1
AN25 / EDS2NB / P40.1 (NC)
L2
VAREF1
P4
VDDM
P3
VSSM / VAGND1
P2
AN36 / EDS1PA / P40.6
J1
AN37 / EDS1NA / P40.7
J2
AN38 / EDS1PB / P40.8
J3
AN39 / EDS1NB / P40.9
J4
AN9
N3
AN15 / EDS3NB
N1
AN14 / EDS3PB
L4
AN33 / P40.5
K2
AN34
K3
AN35
K4
U201E T
C3X6
R222 6R8
CB205 2,2
μ
F
GND
VAREF1
VDDM
R220 1R2 R221 1R2_opt
AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN8 AN10 AN11 AN12 AN13 AN15 AN16 AN17
AN38
PORTS
P13.1
B7
P13.0
A7
P13.3
B8
P13.2
A8
P22.0
J1
1
P32.4 (NC)
P13
P15.8
D7
P33.12
M1
0
P33.13 (NC)
M1
1
P33.0
M9
P00.9
H2
P10.4
B4
P33.1
M8
P33.2
P8
P33.3
N8
NC (P34.2)
N7
NC (P34.3)
P7
P00.12
H1
P00.3
F2
P00.2
F3
P00.1
H4
P15.2
B12
P20.3
G12
P20.6
F11
P00.8
G1
P00.7
G2
P00.6
G3
P02.6
E1
P11.8
D6
P22.3
J1
2
P22.2
H11
P21.0
H12
P23.1
N14
P14.8 (NC)
C7
P14.10 (NC)
C8
NC (P34.1)
M7
P23.3 (NC)
K11
P22.1
L1
2
P10.0 (NC)
C4
U201D T
C3X6
P00.0
GND
Switch ON m
eans t
he
corres
ponding signal is low.
Switch OFF
m
eans t
he
corres
ponding signal is high.
R230 1K5 R232 1K5 R234 1K5 R236 1K5 R240 1K5_opt R238 1K5_opt
P14.5 P14.2 P14.4 P10.5 P10.6 P14.3
HWCFG3 HWCFG4 HWCFG5 HWCFG6
(about configuration see the manual of ass
embled device)
GND
1 2 3 4
8 7 6 5
1
S201 DIPSW-4
R231 47K R233 47K R235 47K R237 4K7 R239 47K R241 47K
V_UC V_UC V_UC V_UC V_UC V_UC
NOTE: S201 is for device configuration
S202 P33.11
R256 1K5
R255 47K
V_STB
Y
GND
DAP 2
AN39
/TRST DAP0 DAP1
D
E
BUG..
R212
33R
R214 0R R215 0R
DAP0 DAP0_A DAP1 DAP1_A
R213 33R
P15.1 P14.1 P14.2 P20.12 P10.5 P10.6
P15.4 P14.0 P15.0
P20.14 P14.4 P14.5
P20.9 P20.10 SYSCLK P33.8 P33.6
P14.3
P33.4 P33.5
P20.7
P20.8
P15.7 P20.11 P20.13 P15.5 P14.6
P33.10 P33.7
VFLE
X
R211 0R
+
3V3
CB203 100n
P14.8
RXD0_P RXD0_N P15.3 T
XD0_P
T
XD0_N
P15.6
P33.9
P14.10
SYSCLK
1
T
XDP
3
GND
2
T
XDN
4
S
RXDP
5
RXDN
6
X201
HSCT0-opt
GND
R254 0R R253 0R R250 0R R251 0R R252 0R
P21.2 P21.5 P21.4 P20.0
P21.3
P11.3 P11.2 P11.6
P33 .1 1
GND
AN36
GND
AN37
GND
AN7
GND
AN24
GND
AN25
R249 4K7 R248 4K7 R244 4K7 R245 4K7 R246 4K7
AN7_I AN24_I AN25_I
AN37_I
AN[0..39]
AN32 AN33 AN35
P02.0 P02.1
P02.2 P02.3
P02.4
P02.5 P02.7 P02.8
P10.1 P10.2 P10.3
P15.2 P15.8
P20.3 P20.6 P22.0 P22.1 P23.3 P32.4 P33.0 P33.1 P33.2 P33.3 P33.12 P33.13
GND
P11.12 P11.10 P11.9 P11.11
P00.1 P00.2 P00.3 P00.6 P00.7 P00.8 P00.9 P00.12 P02.6 P10.0 P13.0 P13.1 P13.2 P13.3
P23.1 P34.1 P34.2 P34.3
P10.4 P11.8
P21.0
P00.5
P00.4
P33.11
AN9 AN14 AN34 AN36_I
P22.2 P22.3
C203 47nF C204 47nF C205 47nF C207 47nF C208 47nF
CB204 470n
CB201 330n
CB202 330n