6ED family - 2nd generation
Technical Description
Application Note
17
Rev. 1.3, 2014-03-23
AN-EICEDRIVER-6EDL04-1
recovers, when the threshold of the integrated Schmitt-trigger according to Figure 12 is reached.This means
that the resistor to
V
CC
is not mandatory, but it may help to precisely adjust the fault-clear time.
The datasheet specifies the typical fault clear time
t
FLTCLR
= 1.9 ms which the current source needs to charge an
external capacitor of 1 nF without pull up resistor. This parameter can be scaled linearly to any other capacitor
value and results immediately in the according fault clear time. This means that e.g. a 4.7 nF capacitor will
realize a fault clear time of 4.7 * 1.9 ms = 8.9 ms.
The design must guarantee that the voltage at capacitor C
RCin
reaches the lower threshold of the RCin-Schmitt-
trigger for the delay time of the input noise filter at pin ITIRP. It is recommended to reach this threshold within
500ns and to use capacitor values which are smaller than 10nF. Otherwise, the flip-flop releases the gate
sections again, so that the IGBT is turned on, which may damage the IGBT.
3.7.3
Deadtime & Shoot Through Prevention
The 6ED family
– 2
nd
generation prevents shoot through and generates a fixed deadtime between the individual
IGBT of each half bridge. The deadtime is typically DT = 310 ns. However, it is necessary to check the transient
times of the driven IGBT. These times are the turn-on delay
t
d(on)
, the rise time
t
r
, the turn-off delay time
t
d(off)
and
the fall time
t
f
. They are defining the timing and the deadtime which is mandatory for the prevention of shoot
through. A deadtime of 1
μs to 1.5 μs is sufficient for most applications.
3.7.4
Undervoltage Lockout (UVLO)
The undervoltage lockout (UVLO) of the highside sections act directly on the output gate drive flipflop according
to Figure 13, so that an immediate shut down is provided. The UVLO is independent in respect of all three
highside gate drive sections. The levels are
V
CCUV+
for the control side and
V
BSUV+
for the high side sections.
Please refer to the correct absolute level in respect to the individual type of the 6ED family. Please refer to
section 3.4 for further information.
In case of an UVLO shut down of an output section, it is necessary to reach the start-up levels of
V
CCUV+
and
V
BSUV+
again as descibed in section 3.4. The independent UVLO functions of low and high side sections enable
a restart of the affected highside section in case of a bootstrapping supply, because the switch mode operation
of the lowside transistor pumps continuously charges into the according bootstrap capacitor, which increases
the bootstrap voltage
V
BS
.
Figure 13
Structure of a lowside UVLO
The UVLO for the lowside gate drive sections is common for all three output circuits and acts on a triple input
OR-gate according to Figure 13. The output of this gate is fed into the deadtime and shoot through prevention of
the IC. Please note here, that a lowside UVLO is also affecting the highside outputs. Hence, all the gate drives
will be shut down in case of a lowside UVLO.
3.8
Calculation of power dissipation and thermal aspects
The 6ED family
– 2
nd
generation is available in two packages, the PG-DSO-28 and the PG-TSSOP-28. Both
packages are RoHS compliant. Please refer to section 3.9 for further information in respect to the insulation
coordination. It is essential to assure, that the component is not thermally overloaded. This can be checked by
means of the thermal resistance junction to ambient and the calculation or measurement of the dissipated
power. The thermal resistance is given in the datasheet (section 5) and refers to a specific layout. Changes of
this layout may lead to an increased thermal resistance, which will reduce the total dissipated power of the
driver IC. One should therefore do temperature measurements in order to avoid thermal overload under
application relevant conditions of ambient temperature and housing.
>1
EN
ITRIP-Latch
UVLO
DEADTIME &
SHOOT-THROUGH
PREVENTION
DEADTIME &
SHOOT-THROUGH
PREVENTION
..
.
..
.
To Highside
To Lowside
To Highside
To Lowside
