CHEETAH Hardware User’s Manual
Imperx, Inc.
Rev. 6.2
6421 Congress Ave.
7/7/2015
Boca Raton, FL 33487
+1 (561) 989-0006
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Figure 1.3 – CLF Camera back panel / Deca, Full, Medium or Base
1.5.2 Camera Link Full Signal Mapping
Camera data output is compliant with Deca (80-bit), Full (64-bit), Medium (48-bit)
and Base (24-bit) Camera Link standard, up to 80 data bits, 4 sync signals (LVAL,
FVAL, DVAL and User Out), 1 reference clock, 2 external inputs CC1, CC2 and a
bi-directional serial interface. The camera link output connectors are shown in
Figure 1.4a and 1.4b, and the corresponding bit and port mapping is described
below.
1
14
13
26
Figure 1.4a – CLF Camera output connector 1
Cable Name
Pin
CL Signal
Type
Description
Base Wire
1
12 VDC Power Power
Power Base
Base Wire
14
Power Return Ground
Ground
- PAIR 1
2
- X 0
LVDS - Out Camera Link Channel Tx
+ PAIR 1
15
+ X 0
LVDS - Out Camera Link Channel Tx
- PAIR 2
3
- X 1
LVDS - Out Camera Link Channel Tx
+ PAIR 2
16
+ X 1
LVDS - Out Camera Link Channel Tx
- PAIR 3
4
- X 2
LVDS - Out Camera Link Channel Tx
+ PAIR 3
17
+ X 2
LVDS - Out Camera Link Channel Tx
- PAIR 4
5
- X CLK
LVDS - Out Camera Link Clock Tx
