CHEETAH Hardware User’s Manual
Imperx, Inc.
Rev. 6.2
6421 Congress Ave.
7/7/2015
Boca Raton, FL 33487
+1 (561) 989-0006
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bottom of the array) during one line time readout. The camera takes care of all the
details of re-ordering the lines within frame grabber memory.
The A/D converter architecture allows the user to select between 8, 10 or 12-bit
digitization. The Cheetah C4080 supports both 10 and 12-bit digitization. In 12-bit
digitization mode, the A/D conversion time is longer than the minimum chip readout
time and this reduces maximum frame rates. In 10-bit digitization the A/D conversion
time is reduced increasing the maximum frame rate. The image sensor provides up to
eight LVDS readout banks and the time to readout one line from the image sensor is
less than the time necessary to output the data using Camera Link. The camera
compensates for this mismatch in data output rates by adding additional delay at the
end of each line.
Each pixel within the imaging array has extremely robust anti-blooming suppression
eliminating classic ‘black sun’ artifacts present in other CMOS imaging arrays. The
CMOS readout architecture also eliminates column smearing often seen in traditional
CCD image sensors under extremely bright exposure conditions.
The time interval required for all the pixels, from the entire imager, to be clocked out
of the CMOS is called a frame. To generate a color image a set of color filters (Red,
Green, and Blue) arranged in a “Bayer” pattern, are placed over the pixels. The
starting color is Green. Figure 1.1 shows the CMOS image sensor architecture. Figures
1.2a,b show the camera’s spectral response.
