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PRELIMINARY

SF104-P01

SF3013M Fingerprint Image Sensor Module User Manual

Page - 35

9.3 Part drawing

9.4 Pin description

Pin Name

Type

Pin Description

INTn Output

An interrupt to the processor can be
generated by finger detection.

SPIDO

(SPIMISO)

Output

Master In Slave Out

VDD Input

System power. Voltage supply for core
operation.

RSTn Input

A LOW on this pin resets the SF104x to take
on its default states

SPICLK Input

The SPI clock rate provided by the master
must not exceed 18MHz. depending on

Содержание SF104x

Страница 1: ...al Page 1 SF104x Fingerprint Image Sensor Module User Manual February 7 2014 Image Match Design Inc http www imagematch com tw B3 2 No 1 Lising 1st Road Hisnchu Science Park Hsinchu 300 Taiwan R O C T...

Страница 2: ...M Fingerprint Image Sensor Module User Manual Page 2 Revision History Version Date Content Approved Checked Drawn P01 2014 02 07 Initial draft Albert Ke P02 2014 3012 I O spec AL P03 2014 03 17 Interf...

Страница 3: ...5 COMMAND CODE DETAIL 13 3 6 REGISTER DETAIL 15 4 OPERATION WORKFLOW 22 4 1 GENERAL DESCRIPTION 22 4 2 RESET 23 4 3 FINGER DETECTION MODE AND INTERRUPT 23 4 4 TIMING CONSIDERATIONS 24 4 5 A SAMPLE SE...

Страница 4: ...PRELIMINARY SF104 P01 SF3013M Fingerprint Image Sensor Module User Manual Page 4 9 5 REFERENCE SCHEMATIC 36...

Страница 5: ...f SF104x is controlled through fingerprint image sensing by pixel array A D converting digital process following is simple interface protocol The captured image quality of SF104x can be adjusted by se...

Страница 6: ...Sensor Module User Manual Page 6 1 3 Sensor Block Diagram 1 4 Applications The compact thin packaging of SF104x sensor module allows a wide range of applications Security devices Fingerprint identifi...

Страница 7: ...13 4mm 13 9mm highly integrated SPI fingerprint module 3 Device operation 3 1 Setting up clock divider The fingerprint sensor module has an on board oscillator of 18Mhz the sensor s internal clock log...

Страница 8: ...6 of OPCLK OPCLK is the system clock pre scaled by 1 16 controlled by REG0 REG_CLK bit 3 0 The detect start clock is controlled by REG9 REG_DDIV bit 7 0 For example given the system clock input of 18M...

Страница 9: ...GA2 gain The ADC bias current and input voltage range is controlled by BIAS VRT VRB and VRB parameters in REG3 REG_ADC See section 5 0 for the detail of the registers 3 3 Command and registers The SF1...

Страница 10: ...OTP address RW 0 5 0x05 reg_otp_wdat OTP wirte data RW 0 otp_wd 6 0x06 reg_otp_mode OTP control RW 0 otp_prg otp_rst otp_ceb 7 0x07 reg_otp_rdat OTP read data RW 8 0x08 reg_deth finger detection thre...

Страница 11: ...L strobe An SF104 command code may or may not have associated data The start and srst commands don t have associated data and take effect immediately after the command code is sent For read write data...

Страница 12: ...read sequence the last command byte is a dummy command write sequence read image sequence In fact except for the write register command which writes a sequence of register content commands can be mixe...

Страница 13: ...st Code 02 START command write only This command starts fingerprint image scan Code 03 status read command read only This command sends the 8 bit internal status flags to host The status flags are def...

Страница 14: ...is for the register content Subsequent register read command can be cascaded in one command sequence Code 0x4N register write command This command starts writing registers starting at address N The fi...

Страница 15: ...ock control 7 6 Test mode 1 00 AREGC 2 01 TESTPIN VREF 10 TESTPIN VINPTST 11 AREGC 0 5 4 Test mode 0 00 AREGC 3 01 TESTPIN VAMP 10 TESTPIN CDS 11 invert ADC data TESTPIN VGND 3 0 DIV_OPCLK The 4 bit D...

Страница 16: ...EN_TEST0 0 Disable Test mode 0 1 Enable Test mode 0 1 0 PGA1_GAIN 00 4 6 01 7 6 10 12 8 11 22 7 REG_DCOC 2 R W 0000_0000 DC_OFFSET DC offset control of PGA2 7 Sign bit 0 negative 1 positive 6 0 Offset...

Страница 17: ...10 16uA default 011 20uA 1xx 24uA 3 2 ADC_VRT VRT VRB settings 00 0 90V 01 1 05V default 10 1 20V 11 1 35V 1 0 ADC_VRB VRB settings 00 0 800V 01 0 844V default 10 0 933V 11 0 978V REG_OTP_A DDR 4 RW 0...

Страница 18: ...control bit Reset 0 OTP_CEB OTP CEB control bit Enable active low REG_OTP_R DAT 7 R OTP read data 7 0 OTP_RDAT OTP read data REG_DETH 8 RW 1111_1111 Detection threshold 7 0 DETH Finger detection thre...

Страница 19: ...scan line detection mode The finger detection scan line can be changed according to value of reg_inscanline 0x11 if enable 0 Disable 1 Enable 5 EN_DET Enable the detect mode 0 Disable 1 Enable 4 Rese...

Страница 20: ...ALOG Enable analog circuit 0 Disable 1 Enable REG_MODE B RW 0000_0000 Mode control bits 7 Not used 6 EN_INTR Enable detect interrupt 0 Disable 1 Enable 5 Not used 4 0 ENBITS Must be set to value 21 0x...

Страница 21: ...REG_LLX REG_LLY REG_URX and REG_URY Refer to following picture to how to set the windowing position and size REG_LLY D RW 0000_0000 Windowing function position setting 7 0 LLY Refer to REG_LLX for det...

Страница 22: ...owing function 4 Operation workflow 4 1 General description The SF104 hardware design implements a protection scheme that fingerprint image will only be delivered when finger touch is detected If not...

Страница 23: ...hardware reset pin the SPI software reset command the reset caused by the content of REG_MODE REG11 register as described earlier However the internal SPI state machine can only be reset by the hardw...

Страница 24: ...nternal image channel will be opened to allow full image data to be transferred to MCU The timing period of detection scan is given by sysclk_freq 4096 REG9 1 If at the end of detect scan the summed p...

Страница 25: ...s about 180 pclk cycles For the subsequent scans the delay time is reduced to 19 pclk cycles Image sample is taken at the speed of pclk i e one pixel per pclk cycle There is a small delay of 11 pclk c...

Страница 26: ...clock REG10 2 1 enable detect REG10 5 1 enable interrupt pin REG11 6 1 spiwrite 0x40 0x32 0xE5 0x50 0x25 0x00 0x00 0x00 0x00 0x00 0x20 0x85 0x15 0x00 0x00 0x9F 0x9F 17 spiwrite 0x50 0x00 2 inform chan...

Страница 27: ...3 repeat byte SPIREAD 0x03 until byte bit0 1 GPIO SSEL 1 read image GPIO SSEL 0 SPISEND 0x01 for i 0 i 160 160 i image i SPIREAD 0x01 GPIO SSEL 1 if checkimage TRUE adjust_setting goto again waiting f...

Страница 28: ...Image Sensor Module User Manual Page 28 until byte bit6 0 wait until DETOK bit goes away GPIO SSEL 1 end of main 5 Timing characteristics 5 1 SPI interface timing General SPI Timing Instruction withou...

Страница 29: ...PRELIMINARY SF104 P01 SF3013M Fingerprint Image Sensor Module User Manual Page 29 Terminating read by applying new command...

Страница 30: ...I_CK clock period during which SPI_CK is low 1 23 ns tSCKH Part of SPI_CK clock period during which SPI_CK is high 1 23 ns tCSCKF Time from falling edge on SPI_CK to edge on SPI_CS_N 1 8 ns tCSCKR Tim...

Страница 31: ...1 Output pin voltage 1 INTn SPIDO 0 3V to VVDDIO 0 3V V TA Operating temperature 20 70 ST Storage temperature 65 150 PT10 Soldering temperature 10 seconds 250 PT120 Soldering temperature 2 minutes 183...

Страница 32: ...ge 0 8 VDD V VIL Low level input voltage 0 2 VDD V IIH High level input current 1 uA IIL Low level input current 1 uA CI Input capacitance 5 pF Digital outputs VoH High level output voltage IOH 1mA 0...

Страница 33: ...rements regarding to environmental durability PARAMETER REFERENCE CONDITIONS Normal Low Limit UNITS Cold operational IEC60068 2 1 Ab 16h 20 0 Hot operational IEC60068 2 2 Bb 16h 85 55 Cold storage IEC...

Страница 34: ...al Page 34 Table 9 3 Requirements for mechanical durability 9 Packaging information 9 1 The SF104 packaging Size 13 4mm 13 9mm 1 1mm with FPC 9 2 Signal definition Pin Description 1 INTn 2 SPIDO SPIMI...

Страница 35: ...on INTn Output An interrupt to the processor can be generated by finger detection SPIDO SPIMISO Output Master In Slave Out VDD Input System power Voltage supply for core operation RSTn Input A LOW on...

Страница 36: ...ter Out Slave In SPICSn Input Chip select for SPI ESD ESD Connect ESD pin to Ground for VDDIO Input System power This voltage is supplied for IO interface operation Normally it can be tied to the VDD...

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