IEI Technology NOVA-300, Руководство пользователя

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The system clock is generated by the AV9155C-02, and the
different CPU clock frequency can be selected by JP3 and
shown as following table:
JP3 1-2 3-4 5-6
8MHz OPEN CLOSE CLOSE
16Mhz CLOSE OPEN CLOSE
20MHz OPEN OPEN CLOSE
25MHz
CLOSE CLOSE OPEN
40MHz CLOSE OPEN OPEN
2.3 System Memory DRAM
The system DRAM on board is divided into two banks, bank 0
and 1. The Bank 0 is the on board optional 4MB DRAM. Bank 1
is the one 72-pin SIMM. Based on the chipset function the 72-pin
SIMM only support single side 16-bit DRAM. There have two
jumpers for the related setting.
•
JP1/JP2 : 4MB DRAM and 72-pin SIMM selection
Function JP1 JP2
On Board 4MB CLOSE CLOSE
72-pin SIMM OPEN OPEN
2.4 Watch-Dog Timer
The Watch-Dog Timer is enabled by reading port 443H. It should
be triggered before the time-out period ends, otherwise it will
assume the program operation is abnormal and will issue a reset
signal to start again, or activate NMI to CPU. The Watch-Dog
Timer is disable by reading port 043H. The Watch-Dog Timer
time-out period can be set 1,2,10,20,110 or 220 sec. by jumper
JP16.
•
JP18 : Watch-Dog Active Type Setting