IEI Technology NANO-KBN-i1, Руководство пользователя, Страница: 66 / 158

NANO-KBN-i1
P a g e 52
4.4.1 Cle a r CMOS Bu tto n
CN La b e l: J _CMOS 1
CN Typ e :
button
CN Lo c a tio n : See Figure 4-3
CN S e ttin g s : See Table 4-2
If the NANO-KBN-i1 fails to boot due to improper BIOS settings, use the button to clear the
CMOS data and reset the system BIOS information.
The clear CMOS button settings are shown in Table 4-2 .
Setting Description
Open Normal Operation Default
Push Clear CMOS Setup
Table 4-2: Clear CMOS Button Settings
The location of the clear CMOS button is shown in Figure 4-3 .
Figure 4-3: Clear CMOS Button Location
4.4.2 LVDS P a n e l Re s o lu tio n S e le c tio n
J u m p e r La b e l: S W1
J u m p e r Typ e :
DIP switch