IEI Technology IOWA-GX, Руководство пользователя

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IOWA-GX CPU Board
Page 13
Split I/D cache/TLB (Translation Look-aside Buffer):
o
16 KB/16 KB caches
o
Efficient Prefetch
Integrated FPU that supports the Intel MMX
®
and AMD
3DNow!™ instruction
sets
Fully pipelined single precision hardware with microcode support for higher
precisions
Branch performance enhanced with Branch Target
Buffer (BTB) and Return
Stack
2.4.2 Memory Controller
The 64-bit DDR memory controller supports a 512MB (maximum) 200MHz DDR
SO-DIMM installed in a 200-pin SO-DIMM socket. The SO-DIMM socket is located on the
solder side of the IOWA-GX.
Figure 2-5: SO-DIMM Socket
2.4.3 Video Processor
The Video Processor mixes the graphics and video streams, and outputs digital RGB data
to the DACs (for CRT display) or the TTL controller (for TFT displays).