IDT Tsi572, Руководство по оборудованию, Страница: 64 / 90

64
Tsi572 Hardware Manual
May 18, 2012
Integrated Device Technology
www.idt.com
3.6.2.1 Interfacing to the S_CLK_x Inputs
The interface for a LVPECL clock source to the receiver input cell is shown in Figure 36 . In the
diagram, an AC-coupled interface is required to ensure only the AC information of the clock
source is transmitted to the clock inputs of the Tsi572.
Two 150 ohm resistors are used in the diagram because LVPECL outputs need DC biasing and a
DC path for the source current. The requirements for DC biasing when interfacing a clock
driver’s output to a CML input should be checked with the suppliers of the clock driver.
Figure 36: LVPECL Clock Source to a Receiver Input Cell
3.6.3 Reset Requirements
The Tsi572 requires only one reset input, HARD_RST_b. The signal provided to the device
must be a monotonic 3.3V swing that de-asserts a minimum of 1mS after supply rails are stable.
The signal de-assertion is used to release synchronizers based on P_CLK which control the
release from reset of the internal logic. P_CLK must therefore be operating and stable before the
1mS HARD_RST_b countdown begins.
The most versatile solution to this requirement is to AND the HARD_RST_b and TRST_b
signals together to form an output to drive the TRST_b pin on the switch.
Power up option pins are double sampled at the release of HARD_RST_b. As such, there is no
set-up time requirement, but the signals must be stable at the release of HARD_RST_b. There is
a hold time requirement of 100nS or 10 P_CLK cycles minimum.
TRST_b must be asserted while HARD_RST_b is asserted following a device
power-up to ensure the correct setup of the tap controller. TRST_b is not required to
be re-asserted for non power cycle assertions of HARD_RST_b
S_CLK_p
S_CLK_n
Clock Source
LVPECL
PCB Traces
150 ohm
150 ohm
100 ohm
0.1uF
0.1uF