22
Tsi572 Hardware Manual
May 18, 2012
Integrated Device Technology
www.idt.com
I2C_SEL
I, CMOS,
PU
I
2
C Pin Select. Together with the I2C_SA[1,0]
pins, Tsi572 will determine the lower 2 bits of the
7-bit address of the EEPROM address it boots
from.
When asserted, the I2C_SA[1,0] values will also
be used as the lower 2 bits of the EEPROM
address.
When de-asserted, the I2C_SA[1,0] pins will be
ignored and the lower 2 bits of the EEPROM
address are default to 00.
The values of the lower 2 bits of the EEPROM
address can be over-ridden by software after
reset.
No termination required.
Internal pull-up may be
used for logic 1.
Pull up to VDD_IO through
10K resistor if an external
pull-up is desired. Pull
down to VSS_IO to
change the logic state.
JTAG TAP Controller
TCK
I, LVTTL,
PD
IEEE 1149.1 Test Access Port Clock input
Pull up to VDD_IO through
10K resistor if not used.
TDI
I, LVTTL,
PU
IEEE 1149.1 Test Access Port Serial Data Input
Pull up to VDD_IO through
a 10K resistor if the signal
is not used or a if higher
edge rate is required.
TDO
O,
LVTTL,
2mA
IEEE 1149.1 Test Access Port Serial Data Output
No connect if JTAG is not
used.
Pull up to VDD_IO through
a 10K resistor if used.
TMS
I, LVTTL,
PU
IEEE 1149.1 Test Access Port Test Mode Select
Pull up to VDD_IO through
a 10K resistor if not used.
TRST_b I,
LVTTL,
PU
IEEE 1149.1 Test Access Port TAP Reset Input
This input must be asserted during the assertion
of HARD-RST_b. Afterwards, it may be left in
either state.
Combine the HARD_RST_b and TRST_b signals
with an AND gate and use the output to drive the
TRST_b pin.
Tie to VSS_IO through a
10K resistor if not used.
Table 3:
Signal Descriptions and Recommended Termination
Pin Name
Type
Description
Recommended
Termination
a
Содержание Tsi572
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