IDT Tsi572, Руководство по оборудованию, Страница: 19 / 90

19
Tsi572 Hardware Manual
May 18, 2012
Integrated Device Technology
www.idt.com
S_CLK_p I,
CML
Differential non-inverting reference clock. The
clock is used for following purposes: SERDES
reference clock, serial port system clock, ISF
clock and test clock.
The maximum frequency of this input clock is
156.25 MHz.
The clock frequency is defined in “Reference
Clock, S_CLK_p/n” on page 35 .
For more information on the S_CLK operating
frequency, refer to
“Line Rate Support” on
page 71 .
AC coupling capacitor of
0.1uF required.
S_CLK_n I,
CML
Differential inverting reference clock. The clock is
used for following purposes: SerDes reference
clock, serial port system clock, ISF clock and test
clock.
The maximum frequency of this input clock is
156.25 MHz.
The clock frequency is defined in “Reference
Clock, S_CLK_p/n” on page 35 .
For more information on the S_CLK operating
frequency, refer to
“Line Rate Support” on
page 71 .
AC coupling capacitor of
0.1uF required.
HARD_RST_b I
LVTTL,
Hyst,
PU
Schmidt-triggered hard reset. Asynchronous
active low reset for the entire device.
The Tsi572 does not contain a voltage detector to
generate internal reset.
Connect to a power-up
reset source.
Refer to “Reset
Requirements” on page 64
Interrupts
INT_b O, OD,
LVTTL,
2mA
Interrupt signal (open drain output) External pull-up required.
Pull up to VDD_IO through
a 10K resistor.
Table 3: Signal Descriptions and Recommended Termination
Pin Name Type Description
Recommended
Termination
a