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IDT Installation of the EB-LOGAN-23 Evaluation Board
89EB-LOGAN-23 Evaluation Board
2 - 10
February 16, 2011
Notes
Power-up Sequence for PES32NT24AG2
During power supply ramp-up, VDDCORE must remain at least 1.0V below VDDIO at all times. There
are no other power-up sequence requirements for the various operating supply voltages.
Heatsink Requirement
The EB-LOGAN-23 evaluation board utilizes a heatsink with integrated fan. All initial shipments of the
board are made with the heatsink whether or not one is truly required. There may be low link usage applica-
tions within which the heatsink may, in fact, not be required.
Reset
The PES32NT24AG2 supports two types of reset mechanisms as described in the PCI Express specifi-
cation:
–
Fundamental Reset: This is a system-generated reset that propagates along the PCI Express
tree through a single side-band signal PERST# which is connected to the Root Complex, the
PES32NT24AG2, and the endpoints.
–
Hot Reset: This is an In-band Reset, communicated downstream via a link from one device to
another. Hot Reset may be initiated by software. This is further discussed in the PES32NT24xG2
User Manual. The EB-LOGAN-23 evaluation board provides seamless support for Hot Reset.
Fundamental Reset
There are two types of Fundamental Resets which may occur on the EB-LOGAN-23 evaluation board:
–
Cold Reset: During initial power-on, the onboard voltage monitor (TLC7733D) will assert the PCI
Express Reset (PERSTN) input pin of the PES32NT24AG2.
–
Warm Reset: This is triggered by hardware while the device is powered on. Warm Reset can be
initiated by two methods:
• Pressing a push-button switch (S3) located on EB-LOGAN-23 board
• The host system board IO Controller Hub asserting PERST# signal, which propagates through
the PCIe upstream edge connector of the EB-LOGAN-23.
Both events cause the onboard voltage monitor (TLC7733D) to assert the PCI Express Reset
(PERSTN) input of the PES32NT24AG2 while power is on.
Downstream Reset
Single Partition Mode without Hot Plug:
When the evaluation board initially powers on, it assumes the following:
The switch is configured in single partition mode.
Slot 0 is the root port and controls the downstream port resets.
Ports 1-23 are downstream ports.
Hot Plug is disabled.
The following behavior should be observed:
The resets to slots 1-23 should initially be asserted and remain this way until after the fundamental
reset is initially de-asserted.
The assertion of slot 0 reset should propagate to slots 1-23.
Stack Configuration
The PES32NT24AG2 contains four stack blocks labeled Stack 0, Stack 1, Stack 2, and Stack 3. Stacks
0 and 1 have four x2 ports each, and stacks 2 and 3 have eight x1 ports each. This provides a total of 24
ports in the device labeled port 0 through port 23. Table 2.11 lists the ports associated with each stack.
Содержание EB-LOGAN-23
Страница 4: ...IDT Table of Contents EB LOGAN 23 Evaluation Board ii February 16 2011 Notes ...
Страница 6: ...IDT List of Figures EB LOGAN 23 Evaluation Board iv February 16 2011 Notes ...
Страница 8: ...IDT List of Tables VB64H16AG2 Validation Board Manual vi February 16 2011 Notes ...
Страница 12: ...IDT Description of the EB LOGAN 23 Evaluation Board 89EB LOGAN 23 Evaluation Board 1 4 February 16 2011 Notes ...
Страница 40: ...IDT Software For EB LOGAN 23 89EB LOGAN 23 Evaluation Board 3 2 February 16 2011 Notes ...
Страница 41: ...Notes EB LOGAN 23 Evaluation Board 4 1 February 16 2011 Chapter 4 Schematics Schematics ...