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IDT Installation of the EB-LOGAN-23 Evaluation Board
89EB-LOGAN-23 Evaluation Board
2 - 8
February 16, 2011
Notes
CLKMODE Selection
All ports in the PES32NT24AG2 device (upstream and downstream) use global clocked mode by
default. The port clocking mode of a port is determined by the state of the CLKMODE[1:0] pins in the boot
configuration vector as shown in Table 2.8. This field determines the initial value of the Slot Clock Configu-
ration (SCLK) field in each port’s PCI Express Link Status (PCIELSTS) register. The SCLK field controls the
advertisement of whether or not the port uses the same reference clock source as the link partner. A one in
the SCLK field indicates that the port and its link partner use the same reference clock source. This is
defined as Common Clock Configuration by the PCI Express Base Specification. A zero in the SCLK field
indicates that the port and its link partner do not use the same reference clock source.
Power Sources
Power for the PES32NT24AG2 and all downstream ports is generated from a 12V supply via an external
power connector. See Table 2.9. A 12V to 3.3V DC-DC converter is used to provide power to five switching
regulators to generate V
DD
CORE, V
DD
PEA, V
DD
PETA, V
DD
PEHA, and V
DD
IO voltages. The 3.3V from the
DC-DC converter will be used to power the clock buffers and circuitries.
The external power supply connectors are 24-pin (J69) and 8-pin (J68) molex connectors as described
in Tables 2.9 and 2.10. The +12V3 is used to power the PES32NT24AG2 and downstream slots 0, 2, 16,
and 20. The +12V2 is used to power downstream slots 4, 6, 8, and 12.
8
J31
[1-3 / 2-4] Onboard Clock Generator (U118)
[3-5 / 4-6] From Clock Buffer (U51) (default)
[7-9 / 8-10] To P08CLK Clock Header (J13)
[9-11 / 10-12] SATA (J31)
12
J32
[1-3 / 2-4] Onboard Clock Generator (U119)
[3-5 / 4-6] From Clock Buffer (U51) (default)
[7-9 / 8-10] To P12CLK Clock Header (J14)
[9-11 / 10-12] SATA (J32)
16
J33
[1-3 / 2-4] Onboard Clock Generator (U120)
[3-5 / 4-6] From Clock Buffer (U51) (default)
[7-9 / 8-10] To P16CLK Clock Header (J15)
[9-11 / 10-12] SATA (J33)
20
J34
[1-3 / 2-4] Onboard Clock Generator (U121)
[3-5 / 4-6] From Clock Buffer (U51) (default)
[7-9 / 8-10] To P20CLK Clock Header (J16)
[9-11 / 10-12] SATA (J34)
SW10[8]
CLKMODE[0]
SW10[7]
CLKMODE[1]
Port 0
SCLK
Port[15:1]
SCLK
ON
ON
0
0
OFF
ON
1
0
ON
OFF
0
1
OFF
OFF
1
1
Table 2.8 CLKMODE Selection PES32NT24AG2
Slot # Jumper
Selection
Table 2.7 EB-LOGAN-23 Slot Clock Select (Part 2 of 2)
Содержание EB-LOGAN-23
Страница 4: ...IDT Table of Contents EB LOGAN 23 Evaluation Board ii February 16 2011 Notes ...
Страница 6: ...IDT List of Figures EB LOGAN 23 Evaluation Board iv February 16 2011 Notes ...
Страница 8: ...IDT List of Tables VB64H16AG2 Validation Board Manual vi February 16 2011 Notes ...
Страница 12: ...IDT Description of the EB LOGAN 23 Evaluation Board 89EB LOGAN 23 Evaluation Board 1 4 February 16 2011 Notes ...
Страница 40: ...IDT Software For EB LOGAN 23 89EB LOGAN 23 Evaluation Board 3 2 February 16 2011 Notes ...
Страница 41: ...Notes EB LOGAN 23 Evaluation Board 4 1 February 16 2011 Chapter 4 Schematics Schematics ...