8A3xxxx 72QFN EVK User Manual
© 2019 Integrated Device Technology, Inc.
15
February 14, 2019
2.3
Output Terminations and Rework to Take 1PPS Input
All outputs are terminated with a 100Ω resistor across the output pair. This is the recommended termination regardless of the Voffset and
Vswing settings. Since the outputs are DC-coupled, they will support a 1PPS output without any need for rework.
Important Equipment Warning
:
When connecting the outputs to measurement equipment, use a DC-block to ensure
that the output operates at its intended V
offset
. Otherwise, the equipment may load the output down and cause degraded
performance.
The following rework must be implemented in order to support a 1PPS input clock. All input clocks for this board are ac-coupled and terminated
as in the following figure.
Figure 13. AC Coupling and Terminations for Input Clock
For a 1PPS input, a single-ended input with DC-coupling is recommended. As such, the populated AC-coupling capacitor must be removed
and the input must be configured as LVCMOS, not differential.
1.
In Figure 13, to make CLK0 supportive of 1PPS input, first configure CLK0 as LVCMOS in Timing Commander (see Figure 14).
Figure 14. Configuring CLK0 as CMOS to Receive a 1PPS Input
2.
Once in LVCMOS mode, CLK0_P and CLK0_N will be two separate LVCMOS inputs instead of a differential pair. To make CLK0_P receive
a 1PPS input, replace C881 with a 0Ω resistor; and at the same time, remove R765 and R770.
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