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REVISION A 09/15/14
82P33714/33814 EVALUATION BOARD
Figure 1. Board Overview
•
OSCI Input and XO –
System reference clock input. Refer to JP9 for clock source selection. The frequency of this input clock
is selected by XO_FREQ[2:0] pins described in SW5.
•
HW Reset button –
Pressing this button will reset the device to default condition.
•
JP9 –
3-pin header used to select the system reference clock to be from OSCI (jump UP) or XO (jump DOWN). Jumper
default position is to jump DOWN to select XO.
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Dip Switch SW5 –
This dip switch contains the following bit configurations:
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Input clock validation control LOS[3:0]
: Once these bits are set, the input clocks will be disqualified (invalid). Please
note: there are other criteria for an input clock to be invalid.
◦
I
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C address bits:
I2C_AD[2:1] sets the lower 3-bit address of 7-bit I2C address with the least significant bit, I2C_AD0
being ignored. Higher 4 bits is fixed at 4'b1010. This only applies to I
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C mode (MPU_MODE[1:0] = 00 in SW6).
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AC/DC Power Jack –
Using a wall adapter AC/DC power supply (output 5VDC/3A with center-positive jack) can power the
board, if 5VDC Power Jack is not supplied with a 5VDC power source.
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5VDC Power Jack –
If AC/DC power source is not used, a 5VDC power source can be plugged into the jack to power the
board. Please note: Power Jacks labeled 3.3V and 1.8V are for other purposes. They can be left unused.
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5VDC Ground Jack –
Paired with 5VDC Power Jack (above) to provide power return when 5VDC bench power supply is
used.
