REVISION A 09/15/14
11
82P33714/33814 EVALUATION BOARD
Figure 13. Output Frequencies Entered after APLL1/APLL2 Configured (example)
◦
Finally, FRSYNC & MRFRSYNC can be configured, if needed. Change FRSYNC & MFRSYNC to 1PPS. By default,
the duty cycle of sync outputs is 50/50. If a pulse is desired, click on the applicable check box. The pulse width is
based on OUT01 clock period.
Figure 14. Configure MRSYNC and MRFRSYNC
8.
Connecting to the Board
. Configurations can be done before making the USB/I
2
C connection to the board. Or,
connecting with the board can be established before configuring. It's recommended to complete initial configurations
before making a USB/I
2
C connection to the board and write registers into the chip.
Note:
after the board connection is
established, any changes to the settings will be automatically written to the respective registers. Follow the steps below
in
Figure 15
to make a connection to the board.
