REVISION A 09/15/14
13
82P33714/33814 EVALUATION BOARD
Figure 16. Frequency Profiles for DPLL
10.Viewing Status – After writing all registers, with configured input reference clocks available, the PLL is supposed to lock
to the reference clock. The PLL operation status can be updated and viewed by clicking “View Status” button in GUI
window. The status window looks like the following (
Figure 17
). Enabled input reference clock will show with a lit LED.
Frequency offset will also be shown. Locking status of the DPLL will be indicated as “Locked” or otherwise as “Free-run”
or “Holdover”. The frequency and phase offset of the output clock with respect to the input reference will be indicated.
