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iO1000 Detailed Service Manual - THEORY OF OPERATION
REDCAP Digital Signal Processor (DSP)
TThe REDCAP SPS 56600 digital signal processor (DSP) contains the new DSP
Engine Ultralite core, which is capable of executing an instruction on every clock
cycle. The DSP56600 consists of the following:
-Data ALU
-Address generation unit
-Program controller
-Program patch detector
-Bus interface unit
-On-chip emulator
-PLL-based clock generator
A standard interface between the DSP56600 core and the on-chip memory and
peripherals support many memory and peripheral configurations.
Serial Peripheral Interface (SPI)
This interface communicates with RF chips using a synchronous serial bus. This
bus includes the following:
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Master Out Slave In (MOSI)
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Master In Slave Out (MISO)
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SPI clock
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Specific chip-select lines
The RCE uses SPI CS2 to select the ODCT, SPI CS1 to select the LV Frac-N, SPI
CS0 to select the ADDAG, SPI CS3 to select the iZIF; and SPI CS4 to select the
GCAP II. The RCE selects one of these chips by driving the chip-select line low
for that chip; it then sends data to the chip using MOSI and the SPI clock. The
RCE also can receive data from the ODCT and ADDAG by clocking it into MISO
using the SPI clock and chip select.
