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THEORY OF OPERATION: Frequency Generator (RF) Section

20

ADDAG ASIC

The ADDAG is an acronym for A/D + D/A + Glue. The ADDAG IC is designed to
be an interface between the system DSP, which is digital, and the custom transmit-
ter and receiver ICs, which are primarily analog.

A 16.8 MHz signal from pin 2 of Y300 Crystal sine_out is routed to pin K9 xtal
input of the LV Frac-N synthesizer. The signal is buffered to produce a 16.8 MHz
reference oscillator.; it goes out pin K6 of the LV Frac-N synthesizer and is routed
to pin A5 of the ADDAG.

The interface to the transmitter consists primarily of two 8-bit D/A converters
with programmable sampling rates and filter bandwidths. The interface to the
receiver consists primarily of a single, 10-bit A/D converter, which is multiplexed
to convert I, Q, and RSSI signals captured from the output of the iZIF IC. The
ADDAG IC includes a D/A converter for PA bias control. The voltage supply cir-
cuit comes from VCC4 and VCC6.

The inputs to the receiver path consist of three sample and hold circuits which are
used to simultaneously sample the I, Q, and RSSI signals coming from the iZIF
IC. To help maximize dynamic range and noise performance, these three input
signals are fully differential, and therefore require a total of six pins on the
ADDAG IC (pins INI, INIB, INQ, INQB, AGC, and AGCB). The sample and hold
circuits are programmed for a 48ksps sampling rate.

After sampling, the three input signals are multiplexed sequentially as differential
signals to a single 10-bit A/D converter. The outputs of the A/D converter are cap-
tured by a shift register, formatted, then sent out as a continuous serial data stream
at the same rate as the internally generated serial clock signal. To make the output
words DSP compatible, they are formatted as fractional, 2’s complement data
words, with the MSB being left justified to turn the 10-bit words from the A/D
converter into 16-bit output words.

The serial output port is designed to produce a 48 kHz frame sync signal (pin
SFS) at the start of each I word transmission. Immediately following the transmis-
sion of the I word, the corresponding bits for the Q and AGC words are sent out in
sequence over the serial port (pin SRD). This corresponds to having an SSI inter-
face which uses a continuous clock in the network mode of operation. The output
serial clock/data rate is 2.4 MHz (pin SCK).

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Содержание F2581A

Страница 1: ...iO1000 Wireless Modem Detailed Service Manual 7 OCT 1999 68P02953C80 O ...

Страница 2: ...y implication estoppel or otherwise any license under the copyrights patents or patent applications of Motorola except for the normal non exclusive royalty free license to use that arises by operation of law in the sale of the product Trademarks The following is a registered trademark of Motorola Inc iDEN Reg U S Pat Tm Off All other trademarks mentioned in this manual are trademarks of their resp...

Страница 3: ...ada Safety Code 6 Antenna and Installation Considerations All equipment must be properly installed in accordance with Motorola installation instructions To assure compliance with United States FCC regulations on RF exposure the user of the equipment must position the antenna in such a way to maintain a separation of at least 8 inches 20 cms between the antenna and the body of any user and nearby p...

Страница 4: ...tory Mutual Approved Sparks in a potentially explosive atmosphere can cause an explosion or fire resulting in bodily injury or even death Note The areas with potentially explosive atmospheres referred to above include fueling areas such as below decks on boats fuel or chemical transfer or storage facilities areas where the air contains chemicals or particles such as grain dust or metal powders and...

Страница 5: ... size shape and deployment area can vary by vehicle make model and front compartment configuration for example bench seat vs bucket seats Contact the vehicle manufacturer s corporate headquarters if necessary for specific air bag information for the vehicle make model and front compartment configuration involved in your communication equipment installation DAMAGED ANTENNAS Do not use any radio pro...

Страница 6: ... expo sure requirements must reflect product usage posi tioning of the iO1000 within the product the type of antenna used the location of the antenna and other factors that may vary with the design and nature of the Final Product Therefore compliance with such FCC requirements can only be determined by an assess ment of the Final Product It is important that any manufacturer to whom the iO1000 mod...

Страница 7: ...attery 40 C to 85 C Channel Spacing 25 kHz Frequency Stability Supply Voltage Frequency Stability Locked to base 0 2 ppm Nominal 3 6 Vdc Locked to base 0 2 ppm Not locked to base 5 ppm Range 3 4 to 3 8 Vdc Not locked to base 5 ppm Sensitivity 10 BER Spurious Emissions Dimensions H x W x D 111 5 x 56 5 x 27 5 mm 851 866 MHz 111 dBm Conducted 43 dBW Weight with lithium battery 126 g Selectivity 25 k...

Страница 8: ...MODEL SPECIFICATIONS FOR F2581A viii ...

Страница 9: ...tion section in the front of this manual Digital Modulation Technology The iO1000 is an 806 866 MHz unit that can operate in three modes dispatch interconnect and multi service It uses two digital technologies Quad 16QAM and Time Division Multiple Access TDMA Quadrature Amplitude Modulation QAM is a modulation technique that trans mits information by altering the amplitude and phase of the radio f...

Страница 10: ...ne for each unit Time allocation enables each unit to transmit its voice information without interference from another unit s transmission Transmission from a unit or base station is accommodated in time slot lengths of 15 milliseconds and frame lengths of 90 milliseconds see Figure 2 on page 3 0 10 20 10 20 Frequency from Desired Channel Center kHz RL 0dBm 10 dB Power dB 10 20 30 40 50 60 70 ...

Страница 11: ...ity Voice compression reduces the number of bits per second while maintaining the voice at an acceptable quality level The iDEN system uses a coding technique called Vector Sum Excited Linear Prediction VSELP to compress voice to 4 2 or 8 0 kbps The compressed voice data bits modulate the RF signal The compres sion rate is based on the type of call dispatch or interconnect and the network configur...

Страница 12: ...annel is created by grouping bursts so that their slot numbers differ by a number referred to as the repetition rate The portable uses two repetition rates for interconnect voice calls 6 1 and 3 1 A single frequency can handle six calls using a 6 1 repetition rate with the 4 2 kbps coder Dispatch calls always use this rate However the audio quality of the 3 1 repetition rate with the 8 0 kbps code...

Страница 13: ...am Description The below figure shows the hardware block diagram of the iO1000 OEM Module This module includes two boards RF and Logic Figure 3 RF and Logic Connection Diagram RF Board The RF board is an 800 MHz RF transceiver It includes frequency synthesizers the transmitter circuitry 0 6 Watt transmit power circuitry receiver circuitry and electronic T R switch LOGIC BOARD RF BOARD RS 232 SB960...

Страница 14: ...F carrier with baseband data signal 2 Receive Demodulation of received RF signal to generate baseband signal 3 Frequency Synthesizer Channels 806 825 MHz TX and 851 870 MHz RX Logic Board The Logic Board includes a red cap that controls the transmit ter receiver and synthesizer operations of the integrated circuits located on the RF board The red cap houses the DSP and the serial communication int...

Страница 15: ...to ADDAG at a rate of 48 K samples per second The ADDAG provides the serial clock to the DSP and a frame sync pulse to tell the DSP to send a sample Each sample is sent as a 16 bit I word followed by a 16 bit Q word and then some meaningless fill bits The I word and the Q word are then converted to an analog differential pair by the ADDAG and amplified The ADDAG also sends a 2 4MHz reference clock...

Страница 16: ...transmitter it incorporates an offset synthesizer and all of the circuitry necessary to implement a cartesian feedback closed loop system The iZIF offset synthesizer phase locks an external VCO at 301 8 MHz This is divided down in the ODCT to 150 9 MHz in the quadrature generator of the internal image reject mixer The divided down offset LO is then mixed with the main LO in the image reject mixer ...

Страница 17: ...DDAG The gain is tuned at the factory and should not require any adjustment any change in the loop gain can result in the transmitter splattering into the adja cent channel The PA is turned on by supplying the battery voltage to pins 3 5 and 7 of the PA through Q501 This is done only after the PA negative bias volt ages have been applied to pins 1 and 4 Coupler At the output of the PA is a high va...

Страница 18: ... AB PA is used for better efficiency and longer battery life The class AB PA is fairly linear but not totally and this causes splatter in the RF spectrum around the transmitted frequency band To reduce splattering into the adjacent channels and to meet sys tem specifications the transmitter uses cartesian feedback to linearize the PA and reduce splatter Negative feedback is a commonly used method ...

Страница 19: ...ERATION Power amplifier Isolator Antenna switch The feedback path includes the following Feedback inductor Attenuator ODCT ASIC Figure 5 Cartesian Loop Amplitude Adjust I Q LO DOWNMIXER 0 90 Phase Adjust 0 90 RF IN UPMIXER RF OUT Transmitter Output ...

Страница 20: ...t signal level from exceeding the ramp level which caused the clip The ramp is allowed to decay to zero Figure 6 Level Set Training Negative feedback is required to maintain system stability Phase training is done to ensure that the feedback is negative 180o The phase shift of the loop consists of the sum of the delays of several modules and components such as SAW filters and amplifiers The Q chan...

Страница 21: ...Figure 8 on page 14 It operates in the commercial portion of the land mobile receiver band 851 866 MHz The receiver takes an incoming RF signal down converts it to a filtered109 65 MHz frequency IF stage and converts it to base band The signal is then digitized The receiver has automatic gain control AGC to maintain good linearity over a wide range of incoming signals The AGC circuitry also preven...

Страница 22: ...put to IF output The mixer LO drive is provided from the VCO buffer in the frequency generation portion of the unit The LO drive is provided to the mixer through a saw filter 3 Pole Crystal Filter The 3 pole crystal filter provides narrow bandpass selectivity centered at the IF frequency 109 65 MHz The crystal filter bandwidth allows a single 21 kHz channel to pass through with little attenuation ...

Страница 23: ...d order intercept point The next stage in the iZIF lineup is the down conversion mixer This is a quadra ture type of mixer Its inputs are the IF and second LO signals see Second Local Oscillator LO on page 19 and its outputs are baseband I and Q signals The last stage in the iZIF is the baseband filters These are lowpass filters that pro vide the IF selectivity for the iZIF Baseband I and Q signal...

Страница 24: ...ich mixes it down to baseband I and Q This information is sent to the ADDAG IC for digitizing prior to sending it to the DSP Frequency Generator RF Section This section contains the following main components in the RF board Low Voltage 3 Volt Fractional N LV Frac N synthesizer Crystal Based Reference Oscillator Circuit Discrete voltage controlled oscillator VCO circuit Second local oscillator LO D...

Страница 25: ...wn LO The output of the detector is the control volt age for the main VCO The feedback loop keeps the receive and transmitter fre quencies locked and allows frequency transitions in a short period of time lock time less than 3 milliseconds The LV Frac N controls the power to the main VCO and buffer circuitry in bat tery save mode It switches the superfilter supply to the VCO and buffer on and off ...

Страница 26: ...r the other synthesizers The crystal based reference oscil lator temperature compensation and frequency error correction is provided by the LV Frac N synthesizer This 16 8 MHz signal is sent to all the ICs iZIF ADDAG DSP ODCT as a reference 16 8MHz Reference Oscillator Y300 D300 SPI Bus VCP vmult1 vmult2 1 05MHz Regulated VCP Supply CR301 CR302 Q301 LV Frac N U301 Phase Detect Loop Divider Prescal...

Страница 27: ...xer inside the iZIF in the receiver lineup see iZIF IC on page 15 The second LO consists of a VCO loop divider phase detector reference fre quency and loop filter The loop divider and phase detector are internal to the iZIF The reference frequency is obtained by taking the 16 8 MHz crystal refer ence signal into pin 21 of the iZIF and then dividing it down inside the IC to get 2 1 MHz The loop fil...

Страница 28: ...Q and RSSI signals coming from the iZIF IC To help maximize dynamic range and noise performance these three input signals are fully differential and therefore require a total of six pins on the ADDAG IC pins INI INIB INQ INQB AGC and AGCB The sample and hold circuits are programmed for a 48ksps sampling rate After sampling the three input signals are multiplexed sequentially as differential signal...

Страница 29: ...ircuitry DC voltage distribution Audio circuitry Digital REDCAP and associated circuitry Transmitter path Receiver path Frequency generating RF The keypad contains the high audio speaker microphone and keypad circuitry Global Control Audio Power II GCAP II Circuitry The GCAP II integrated circuit IC contains the following Two BUCK BOOST switching power supplies 2 775Vdc 5 0Vdc regulator 3 0Vdc 5 0...

Страница 30: ...heral interface read write interface Auxiliary battery switch control 100 pin dual die QFP IC package The GCAP II IC is designed to support the needs of portable cellular telephone products It provides the necessary control audio and regulator functions The following functions are provided Turn on control signals to properly activate the unit Turn off control signals to turn off the unit if an err...

Страница 31: ...gulator supplies 1 875Vdc to the DSP and MCU cores Additionally an external 3 0Vdc linear regulator on the logic board supplies power to the accessories Several sections of the radio are connected directly to the external power supply which supplies Raw_B and Fused_B The external power supply is connected to the accessory connector J4 pins 19 through 23 and 26 through 30 These pins supply the Raw_...

Страница 32: ... REG V1 2 775V 60mA GCAP II LINEAR REG V3 1 875V 120mA GCAP II Vref tracks V2 2 775V 5mA Fuse LM2981 3 0V 100mA RAW_B Raw_B LM2664 2 775V Inverter ODCT Super Filter 2 775V 30mA Drain Switch ODCT Up mixer iZIF LVFrac N Mixer VCO ADDAG FLASH SRAM Redcap QVccH Accessory Vdd Ext Memory Bus SPI and ESSI Ports REDCAP DSP MCU CORE Filt_B Fused_B Filt_B Fused_B Vcc2 Vcc2 Vcc6 Vcc2 Vcc4 Vcc3 Clock Buffers ...

Страница 33: ... core for further processing Received analog signals are converted to digital signals by the ADDAG then sent to the DSP for processing The DSP then sends the processed signals to the CODEC where they are converted from digital to an analog audio signal in the DAC The DAC output is low pass filtered to attenuate any out of band noise From this point the audio signal is sent to the GCAP II output am...

Страница 34: ...he integrated circuits located in the RF section Within the REDCAP is the DSP and the serial communication interface The digital section contains the following Figure 13 REDCAP Power On Off circuitry Serial peripheral interface SPI Host memories flash and SRAM Accessory Connector GCAP II and its circuitry 60 pin interface connector to the main board Table 1 Audio Amplifier Outputs Device Outputs N...

Страница 35: ...SC archi tecture high performance and high code density SPS 56600 NDE UL DSP core running up to 58 8 MHz at 1 8Vdc Fully programmable PLL for system clock generation with low output clock drivers FLASH U802 SRAM U803 GCAP II U001 Integrated Audio and DC Voltage Converter Regulator 30 pin ZIF CONNECTOR J4 TO TRANSCEIVER RF BOARD REDCAP U801 DSP RAM ROM MDI RAM ROM MCU SAP TIMER BBP L1 Timer TIMER U...

Страница 36: ...pheral interface to communicate with external peripherals Serial communications interface with baud rate generator up to 525 kbps On chip Emulator OnCE integrated with JTAG port compliance Interrupt general purpose I O and keypad interface pins Very low power CMOS design Wait stop and doze low power standby modes ...

Страница 37: ...ial Port BBP Counter Audio CODEC Serial Port SAP DSP Timer BRM QSPI SIM External Interface Module RESET RAM 512 x 32 ROM 4k x 32 MCU Timers PWM PIT Watchdog MCU Core Peripheral I F Gaskat PIG GPReg DSP_IRQ YROM 9Kx16 YRAM 8Kx16 XROM 9Kx16 XRAM 7Kx16 Shared X MCU RAM1Kx16 Clocks PLL Layer 1 Timer MCU Debug JTAG OnCE UART MUX PROM 48K x 24 24K x 24 PRAM 512 x 24 24K x 24 CKIH CKIL CKOH CKO TOUT 8 DE...

Страница 38: ...unit When the ON OFF pin J4 17 is held high the GCAP II turns on The GCAP internal low voltage detector provides the initial active low reset to the RISC microprocessor MCU After the VCC3 arrives at the digital section the MCU takes over and drives the reset out line low until its internal PLL locks At this point the MCU begins running the subscriber code The MCU asserts the CS1 signal to a high l...

Страница 39: ...ripherals support many memory and peripheral configurations Serial Peripheral Interface SPI This interface communicates with RF chips using a synchronous serial bus This bus includes the following Master Out Slave In MOSI Master In Slave Out MISO SPI clock Specific chip select lines The RCE uses SPI CS2 to select the ODCT SPI CS1 to select the LV Frac N SPI CS0 to select the ADDAG SPI CS3 to selec...

Страница 40: ...then both EB0 and EB1 are driven low Accessory Connector Signal MUX The RCE uses the three serial protocols UART SB9600 and JTAG to communi cate to external devices through the bottom connector of the unit There is no external hardware for switching from one protocol to another because the REDCAP handles the switching and line multiplexing functions internally Clock Buffers High frequency clock 16...

Страница 41: ... 8 MHz and the DSP PLL is programmed to generate a higher operating frequency The DSP PLL runs at 58 8 MHz Host System Clock Synthesizer During initial power up the host system clock RCE is synthesized from the 32 768 kHz crystal via the GCAP II using the built in GCAP PLL The host microprocessor s system clock is then referenced from the LV Frac N 16 8 MHz reference The RCE programmable interrupt...

Страница 42: ...EM 11 AUDIO _COMMON Analog Ground 12 AUDIO_OUT OUT Audio Out from OEM 13 OPT_SELECT_1 I O 10 27K pull up OEM Configuration 14 OPT_SELECT_2 I O 10 27K pull up OEM Configuration 15 MUX_CNTL IN 100K pull down Logic 0 Manufacture use 16 Option _3V Regulated 3 V Output 17 OEM ON OFF IN Power On OFF 18 MOD In 22K pull down Programming signal 19 BAT_VCC 3 6V OEM operation voltage 20 BAT_VCC Supply Voltag...

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