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4.7 Advanced Chipset Features
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Software
Advanced Chipset Features
SDRAM CAS Latency Time
SDRAM Cycle Time Tras/Trc
SDRAM RAS-to-CAS Delay
SDRAM RAS Precharge Time
System BIOS Cacheable
Video BIOS Cacheable
Memory Hole At 15M-16M
CPU Latency Timer
Delay Transaction
AGP Graphics Aperture Size
Use VGA BIOS In VBU Block
On-Chip Video Window Size
Output Device Priority
3
7/9
3
3
Disabled
Disabled
Disabled
Disabled
Enabled
64MB
Enabled
64MB
CRT/FP/TV
Item Help
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Move Enter: Select +/-/PU/PD: Value F10:Save ESC: Exit
F1:General Help
F5:Previous Values F6:Fail-safe defaults F7:Optimized Defaults
This section allows you to configure the system based on the
specific features of the installed chipset. This chipset manages
bus speeds and access to system memory resources, such as
DRAM and the external cache. It also coordinates
communications between the conventional ISA bus and the PCI
bus. It must be stated that these items should never need to
be altered. The default settings have been chosen because
they provide the best operating conditions for your system.
DRAM Settings
The first chipset settings deal with CPU access to dynamic
random access memory (DRAM). The default timings have
been carefully chosen and should only be altered if data was
lost. Such a scenario occur if your system had mixed speed