ICP Electronics NOVA-7896, Руководство пользователя

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NOVA-7896/7896FW Socket 370 Celeron
TM
& Pentium III
®
Multimedia & Dual Ethernet ,IEEE1394, Embedded Board
47
Advanced DRAM Control 1 / 2 Settings
The first chipset settings deal with CPU access to dynamic random
access memory (DRAM). The default timings have been carefully
chosen and should only be altered if data is being lost. Such a scenario
might well occur if your system had mixed speed DRAM chips installed
so that greater delays may be required to preserve the integrity of the
data held in the slower memory chips.
Auto Configuration
This item will automatically configure the chipset timing. . You may select
'manual' to set up following gray items by your specific need.
The choice: Manual, Auto, 100MHZ, 133MHZ.
SDRAM RAS Active Time
This item defines SDRAM ACT to PRE command period.
The Choice: 6T, 7T, 5T, 4T.
SDRAM RAS Precharge Time
This item defines SDRAM PRE to ACT command period.
The Choice: 3T, 2T, 4T, Reserved.
RAS to CAS Delay
This item defines SDRAM ACT to Read/Write command period.
The choice: 3T, 2T, 4T, Reserved.
Dram Backgroud Command
This item is lead-off time control for DRAM background command. When select
'Delay 1T' , background commands are issued 1 clock behind memory address
(MA) been issued. When select 'Normal', background command and MA are
issued at the same time.
The choice: Delay 1T, Normal.