NOVA-7896/7896FW Socket 370 Celeron
TM
& Pentium III
®
Multimedia & Dual Ethernet ,IEEE1394, Embedded Board
49
Mem Command Output Time
This item is to control the timing to drive memory command onto memory bus.
The choice: Normal, Delay 1T.
SDRAM/VCM CAS Latency
When synchronous DRAM is installed, the number of clock cycles of CAS
latency depends on the DRAM timing.
The Choice: 2, 3 , SPD
SDRCLK Control
This item controls the phase of SDRCLK that lags behind SDCLK.
The choice: Enabled, Disabled.
SDWCLK Control CS#/CKE
This item controls the phase of SDWCLK used for chip set select signals pin
that lags ahead SDCLK.
The choice: Enabled, Disabled.
SDWCLK Control MA/SRAS
This item controls the phase of SDWCLK used for MA/ SRAS signals that lags
ahead SDCLK.
The choice: +5.0ns~-2.5ns (Default 0.0ns)
SDWCLK Control DQM/MD
This item controls the phase of SDWCLK used for DQM/MD signals that lags
ahead SDCLK.
The choice: +5.0ns~-2.5ns (Default 0.0ns)
Содержание NOVA-7896
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