IBM Z9, Руководство по планированию

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Central Processors
Central processors (CPs) can be dedicated to a single LP or shared among multiple
LPs. CPs are allocated to an LP when the LP is activated. You can use operator
tasks to limit and modify the use of CP resources shared between LPs while the
LPs are active.
Multiple Image Facility
The multiple image facility (MIF) is available on all CPCs discussed in this
publication. MIF allows channel sharing among LPs. For information about
accessing devices on shared channel paths and defining shared channel paths, see
“Defining Shared Channel Paths” on page 3-48.
MCSS: Multiple Logical Channel Subsystems (CSS) are available on all CPCs
discussed in this publication. Each CSS supports a definition of up to 256 channels.
Channel Paths: Active LPs can share channels. Shared channels require that the
channel subsystem establish a logical path for each channel image corresponding
to an active LP that has the channel configured online. CNC, CTC, OSC, OSD,
OSE, OSN, CBP, CFP, CIB, ICP, FC, FCV, FCP, and IQD channel path types can
be shared. CVC and CBY channel paths cannot be shared.
For information about accessing devices on shared channel paths and defining
shared channel paths, see “Defining Shared Channel Paths” on page 3-48.
Crypto Features
An optional feature, Crypto Express2, is available, which is designed for Federal
Information Processing Standard (FIPS) 140-2 Level 4 Certification. Crypto
Express2 contains two PCI-X adapters, each of which can be configured
independently as either a coprocessor or an accelerator. The default is coprocessor.
Crypto Express2 can be configured using the Cryptographic Configuration panel
found under the Configuration tasks list.
Crypto Express2 Coprocessor (CEX2C) replaces the functions of the PCI X Crypto
Coprocessor (PCIXCC), which was available on some previous zSeries processors,
such as the z890 and z990.
Crypto Express2 Accelerator (CEX2A) replaces the functions of the PCI Crypto
Accelerator (PCICA), which was available on some previous zSeries processors
such as the z890 and z990.
Crypto Express2 Coprocessor is used for secure key encrypted transactions, and is
the default configuration. CEX2C:
v
Supports highly secure cryptographic functions, use of secure encrypted key
values, and User Defined Extensions (UDX).
v
Is designed for Federal Information Processing Standard (FIPS) 140-2 Level 4
certification.
Crypto Express2 Accelerator is used for SSL acceleration. CEX2A:
v Supports clear key RSA acceleration.
v
Offloads compute-intensive RSA public-key and private-key cryptographic
operations employed in the SSL protocol.
Chapter 1. Introduction to Logical Partitions
1-3
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