IBM REDPAPER 520Q, Технический обзор и введение

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© Copyright IBM Corp. 2006. All rights reserved.
25
Chapter 2.
Architecture and technical
overview
This chapter discusses the overall system architecture of the p5-520 and p5-520Q. Figure 2-1
details the base system hardware and the DCM or QCM options. (You cannot mix an
installation of DCM and QCM options.) The bandwidths in this chapter are theoretical
maximums that are provided for reference. We always recommend that you obtain real-world
performance measurements using production workloads.
Figure 2-1 IBM System p5 520 and IBM System p5 520Q architecture with QCM or DCM
2
Enhanced
I/O Controller
GX+
700
MHz
(DCM)
Re
m
o
te
I/O ca
rd
RIO-2 bus 2B (Diff’l)
Each direction @ 1GB/s
Service Processor
Two SPCN ports
P1-C7-T3 T4 System Ports
P1-T1 T2 HMC ports
P1-C7-T1 T2 Rack Indicator Light
cable port P1-T9
CoD key card
buzz interface
USB ports
P1-T7 T8 Ethernet ports
P1-T5 T6
USB
32-bit
Dual 1GB
Ethernet
64-bit
P
C
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1,
6
4
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2
,
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-b
it,
6
6
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z,
3
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v
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lt
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3
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5,
6
4
-b
it
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133
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, 3.
3 v
o
lt
s
Short Long Long Short Short
PCI-X to PCI-X
bridge 0
133
MHz 33
MHz
PCI-X to PCI-X
bridge 3
IDE
controller
133 MHz 64-bit
Dual SCSI
Ultra320 64-bit
RAID enablement
card
4-pack disk drive backplane
P2-T15-L15-L0 4-pack disk drive backplane
P3-T14-L15-L0
Tape drive
P4-D1
Optional media backplane
Slim-line media device
Slim-line media device
Operator panel
P1-C1 C2 C3 C4 C5
P
2-
T
1
1-
L8-
L0
P
2-
T
1
1-
L5-
L0
P
2-
T
1
1-
L4-
L0
P
2-
T
1
1-
L3-
L0
P2
-D
1
P2
-D
2
P2
-D
3
P2
-D
4
P3
-D
1
P3
-D
2
P3
-D
3
P3
-D
4
P
3-
T
1
1-
L8-
L0
P
3-
T
1
1-
L5-
L0
P
3-
T
1
1-
L4-
L0
P
3-
T
1
1-
L3-
L0
2x4 B @
633 MHz
66 MHz
32-bit
PO
W
ER5+
co
re
2.
1 GH
z
PO
W
ER5+
co
re
2.
1 GH
z
PO
W
ER5+
co
re
2.
1 GH
z
PO
W
ER5+
co
re
2.
1 GH
z
1
.9 M
B
S
h
ar
e
d
L2 c
ac
he
L3
Ctrl
Me
m
Ct
rl
DCM
E
nhanc
ed
d
is
tr
ibu
te
d
sw
it
ch
SMI-II SMI-II
1056 MHz
2x8 B for read
2x8 B for write
D
IMM C
X
J
X
X
“
A
x
”
D
IMM C
X
J
X
X
“
A
x
”
D
IMM C
X
J
X
X
“
A
x
”
D
IMM C
X
J
X
X
“
A
x
”
D
IMM C
X
J
X
X
“
A
x
”
D
IMM C
X
J
X
X
“
A
x
”
D
IMM C
X
J
X
X
“
A
x
”
D
IMM C
X
J
X
X
“
A
x
”
2x8 B
@528 MHz
36
M
B
L
3
ca
che
2x16 B
@1.05 GHz
QCM
2x
1
6
B
@
825
M
H
z
SMI-II SMI-II
1056 MHz
2x8 B for read
2x8 B for write
D
IMM C
X
J
X
X
“
A
x
”
D
IMM C
X
J
X
X
“
A
x
”
D
IMM C
X
J
X
X
“
A
x
”
D
IMM C
X
J
X
X
“
A
x
”
D
IMM C
X
J
X
X
“
A
x
”
D
IMM C
X
J
X
X
“
A
x
”
D
IMM C
X
J
X
X
“
A
x
”
D
IMM C
X
J
X
X
“
A
x
”
36 M
B
L3 c
ac
he
2x
1
6
B
@
825
M
H
z
36 M
B
L3 c
ac
he
Core
1.65 GHz
Core
1.65 GHz
1.
9 M
B
L2 cache
1.
9 M
B
L2 cache
L3
ctrl
L3
ctrl
Mem
ctrl
Mem
ctrl
E
nhanced
d
ist
ri
but
ed s
w
it
ch
E
nhanced
dist
ri
but
ed s
w
it
ch
Core
1.65 GHz
Core
1.65 GHz
To Enhanced I/O Controller To Enhanced I/O Controller
P
C
I-
X
sl
ot
6,
6
4
-b
it
,
133
M
H
z
, 3.
3 v
o
lt
s
Long
C6
2x8 B
@528 MHz