IBM F16, Руководство пользователя

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destination port sends a transmission complete message (a Finish message) to the
port that received the frame. This method allows the receiving port to reuse the
buffer for subsequent frames received.
The central memory is also incorporated into the ASICs. Frames received on the
ports in an ASIC are written into the portion of central memory in the receiving chip.
Received frames cannot be written into the sections of central memory located in
other ASICs. All transmitters in a 2109 Model F16 switch can read from the
memories in any of the ASICs, through inter-chip connections clocked at 106.25
MHz.
Each ASIC contains RAM devices plus data path crossbar logic that is used to
implement the central memory. Memory blocks are accessed in a time-sliced
fashion. The buffer pool can be split into 2112-byte buffers or into 312-byte
mini-buffers. If frames that need to be buffered are smaller than the maximum 2112
bytes, using mini-buffers effectively expands the buffer pool and increases the
efficiency of memory usage by providing more (but smaller) receive buffers.
Additionally, the Bloom ASIC provides a special memory interface (SMI). The SMI
provides the firmware with a mechanism to read and write frame contents to and
from the ASIC. It also supports higher throughput transfers. The SMI includes a set
of two buffers that are large enough for an entire maximum-sized frame to be
transferred in a single operation. Additionally, because two buffers are available, the
firmware can perform a read or write on a frame in one of the buffers while the
ASIC streams another frame into the other buffer.
ASICs
Two ASICs within the system provide the switching functionality. Each ASIC
provides eight Fibre Channel ports that you can use to connect to external node
ports (N_ports) (as an F_port), external loop devices (as an FL_port), or to other
3534 or 2109 series boxes (as an E_port).
Each port can operate at either 1.0625 Gbps or 2.125 Gbps link speeds. The ASIC
contains the Fibre Channel interface logic, message and buffer queuing logic,
receive buffer memory for the eight on-chip ports, and other support logic.
The Bloom ASICs are PCI slaves to the CPU. The two ASICs interface through an
inter-chip 10-bit SSLT2 bus connection clocked at 106.25 MHz. A 16-channel
SERDES is used to support 16 ports. The interface between ASIC and SERDES is
also a 10-bit SSTL2 bus running at 106.25 MHz. The SERDES converts the 10-bit
wide parallel data from the SSTL2 bus into high-speed serial data for the SFP
media and vice versa. The SERDES supports single data rate (SDR) or double data
rate (DDR) transfer between the SERDES and the SFP media. The DDR operation
supports 2.125 Gbps data transfer rate between ASICs. Implementing the SERDES
external to the ASIC reduces the risk of silicon packaging as well as the risk of
running 2.125 Gbps signals on a board with a long trace length.
The SFP media interfaces to external devices and enables support for shortwave
laser and longwave laser. Two LEDs for each port provide port status and link
speed information.
Control Message Interface: The 2109 Model F16 Control Message Interface
(CMI) consists of a set of control signals that are used to pass hardware-level
messages between ports. Recipient ports use these control signals to inform
transmitting ports when a new frame needs to be added to the output queue of the
transmitter. Transmitting ports also use the CMI to inform recipient ports that a
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IBM TotalStorage SAN Switch: 2109 Model F16 User’s Guide