HT82M75REW/HT82K75REW
Rev. 1.00
51
June 11, 2010
RF Transceiver Memory Block
The Memory Block of the RF Transceiver is imple-
mented by the SRAM. As the following Memory Block
diagram shown, the RF Transceiver Memory is com-
posed of registers and FIFOs, which can be accessed
by the SPI interface. They are categorized into two kinds
of address spaces. One is the short address space; the
other is the long address space.
Registers
Registers provide control bits and status flags for the RF
Transceiver operations, including transmission, recep-
tion, interrupt control, MAC/baseband/RF parameter
settings, etc. The registers are divided into two types ac-
cording to addressing mode as listed below.
·
Short address register (6-bit short addressing mode
register, total 64 registers)
·
Long address register (10-bit long addressing mode
register, total 128 registers)
Short address registers are accessed by short address-
ing mode with valid addresses ranging from 0x00H to
0x3FH. Long address registers are accessed by long
addressing mode with valid addresses ranging from
0x200H to 0x27FH. Short registers are accessed faster
than long registers. Please refer to the following SPI In-
terface section for detailed addressing rules via SPI in-
terface.
Memory Space Diagram
Memory Block Diagram
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