Rev. 1.00
94
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Rev. 1.00
95
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HT66FM5440
Brushless DC Motor A/D Flash MCU
HT66FM5440
Brushless DC Motor A/D Flash MCU
A/D Converter Data Registers – ADRL, ADRH, ISRLn, ISRHn
As this device contains an internal up to 12-bit A/D converter, it requires two data registers to store
each converted value. These are a high byte register, known as ADRH, and a low byte register,
known as ADRL, to store the converted value which is triggered by the ADSTR bit. The device
also contains four register pairs to strore the converted value which is triggered by the DLSTR bit.
Each register pair is composed of a high byte register, known as ISRHn, and a low byte register,
known as ISRLn. After the conversion process takes place, these registers can be directly read by the
microcontroller to obtain the digitised conversion value. As only 12 bits or 10 bits of the 16-bit register
space is utilised, the format in which the data is stored is controlled by the ADRFS bit in the ADCR0
register together with the ADCRL_SEL bit in the ADCR2 register as shown in the accompanying
table
s
. D0~D11 or D0~D9 are the A/D conversion result data bits. Any unused bits will be read as
zero.
• ADCRL_SEL=0 → 12-bit Format
ADRFS
ADRH (Read only)
ADRL (Read only)
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
D11 D10 D9 D� D� D6 D5 D4 D3 D� D1 D0
0
0
0
0
1
0
0
0
0
D11 D10 D9 D� D� D6 D5 D4 D3 D� D1
D0
ADRFS
ISRHn (Read only)
ISRLn (Read only)
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
D11 D10 D9 D� D� D6 D5 D4 D3 D� D1 D0
0
0
0
0
1
0
0
0
0
D11 D10 D9 D� D� D6 D5 D4 D3 D� D1 D0
Note: n=0~3
• ADCRL_SEL=1 → 10-bit Format
ADRFS
ADRH (Read only)
ADRL (Read only)
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
D9 D� D� D6 D5 D4 D3 D� D1 D0
0
0
0
0
0
0
1
0
0
0
0
0
0
D9 D� D� D6 D5 D4 D3 D� D1 D0
ADRFS
ISRHn (Read only)
ISRLn (Read only)
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
D9 D� D� D6 D5 D4 D3 D� D1 D0
0
0
0
0
0
0
1
0
0
0
0
0
0
D9 D� D� D6 D5 D4 D3 D� D1 D0
Note: n=0~3
A/D Converter Data Registers
A/D Converter Boundary Registers – ADLVDL, ADLVDH, ADHVDL, ADHVDH
The device contains what are known as boundary registers to strore fixed values for comparison
with the A/D converted data value stored in ADRH/ADRL or ISRHn/ISRLn. There are two pairs of
boundary registers, a high boundary pair, known as ADHVDL and ADHVDH, and a low boundary
pair known as ADLVDL and ADLVDH. Only the converted data of OPA0O, OPA1O or OPA2O,
which are stored in ADRH/ADRL or ISRHn/ISRLn, can be compared with the low and high
boundary values.
As only 12 bits or 10 bits of the 16-bit register space is utilised, the format in which the data is
stored is controlled by the ADRFS bit in the ADCR0 register together with the ADCRL_SEL bit in
the ADCR2 register as shown in the accompanying table
s
.
