Rev. 1.10
32
March 02, 2020
Rev. 1.10
33
March 02, 2020
BS83A02L/BS83B04L
Ultra-Low Power Touch Key Flash MCU
BS83A02L/BS83B04L
Ultra-Low Power Touch Key Flash MCU
3. Ensure that the write operation is totally complete before changing the EEC register
content.
Reading Data from the EEPROM
To read data from the EEPROM, the EEPROM address of the data to be read must first be placed in
the EEA register. The read enable bit, RDEN, in the EEC register must then be set high to enable the
read function. If the RD bit in the EEC register is now set high, a read cycle will be initiated. Setting
the RD bit high will not initiate a read operation if the RDEN bit has not been set. When the read
cycle terminates, the RD bit will be automatically cleared to zero, after which the data can be read
from the EED register. The data will remain in the EED register until another read or write operation
is executed. The application program can poll the RD bit to determine when the data is valid for
reading.
Writing Data to the EEPROM
To write data to the EEPROM, the EEPROM address of the data to be written must first be placed in
the EEA register and the data placed in the EED register. To initiate a write cycle, the write enable
bit, WREN, in the EEC register must first be set high to enable the write function. After this, the
WR bit in the EEC register must be immediately set high to initiate a write cycle successfully. These
two instructions must be executed in two consecutive instruction cycles. The global interrupt bit
EMI should also first be cleared before implementing any write operations, and then set high again
after the write cycle has started. Note that setting the WR bit high will not initiate a write cycle if
the WREN bit has not been set. As the EEPROM write cycle is controlled using an internal timer
whose operation is asynchronous to microcontroller system clock, a certain time will elapse before
the data will have been written into the EEPROM. Detecting when the write cycle has finished
can be implemented either by polling the WR bit in the EEC register or by using the EEPROM
interrupt. When the write cycle terminates, the WR bit will be automatically cleared to zero by the
microcontroller, informing the user that the data has been written to the EEPROM. The application
program can therefore poll the WR bit to determine when the write cycle has ended.
Write Protection
Protection against inadvertent write operation is provided in several ways. After the devices
are powered-on the Write Enable bit in the control register will be cleared preventing any write
operations. Also at power-on the Bank Pointer, BP, will be reset to zero, which means that Data
Memory Bank 0 will be selected. As the EEPROM control register is located in Bank 1, this adds a
further measure of protection against spurious write operations. During normal program operation,
ensuring that the Write Enable bit in the control register is cleared will safeguard against incorrect
write operations.
EEPROM Interrupt
The EEPROM write interrupt is generated when an EEPROM write cycle has ended. The EEPROM
interrupt must first be enabled by setting the DEE bit in the relevant interrupt register. When an
EEPROM write cycle ends, the DEF request flag will be set. If the EEPROM interrupt is enabled
and the stack is not full, a jump to the associated EEPROM Interrupt vector will take place. When
the interrupt is serviced, the EEPROM interrupt request flag, DEF, will be automatically reset and
the EMI bit will be automatically cleared to disable other interrupts. More details can be obtained in
the Interrupt section.