QSG-5200
5
Holt Integrated Circuits
MII (Media Independent Interface) Default Configuration
The MII interface is defined by Clause 22 of the IEEE 802.3 Specification. The HI-5200 PHY evaluation
board receives power and accesses MII data and management information from the MII connector J1. In
MII mode, the PHY is clocked at 25 MHz. A crystal oscillator on the board provides the clock, or an
external 25MHz clock can be connected to the XI pin.
MII Management (MIIM) is conducted thru pins MDC (clock line) and MDIO (data line). MIIM allows
upper-layer devices to monitor and control the states of the HI-5200. An external device with
MDC/MDIO capability can read the PHY status or configure/write the PHY registers. The MIIM frame
format and timing information can be found in the HI-5200 Datasheet and in Clause 22 of the IEEE 802.3
Specification.
The HI-5200 PHY board has a bottom-side 50-pin connector J1 for MII connection. Table 1 lists the pin-
outs for the MII interface on connector J1.
Table 1. Connector J1 Fast Ethernet Port MII Pin Definition.
J1 Pin #
Signal
J1 Pin #
Signal
1
--
2
--
3
--
4
--
5
+5V
6
+5V
7
MDIO
8
GND
9
MDC
10
GND
11
RXD3
12
GND
13
RXS2
14
GND
15
RXD1
16
GND
17
RXD0
18
GND
19
RXDV
20
GND
21
RXCLK
22
GND
23
RXER
24
GND
25
TXER
26
GND
27
TXCLK
28
GND
