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QSG-5200 

 

11 

 

Holt Integrated Circuits 

Test Point Definition 

The HI-5200 ADK PHY evaluation board has six test points. They are defined in the following table.  

Table 5. HI-5200PC PHY Evaluation Board Test Points. 

Test Point  Description 

TP1 

Interrupt Signal (U1 pin 21) with external pull-up 

TP2 

Signal Ground 

TP3 

Signal Ground 

TP20 

+5VDC input DC voltage check 

TP21 

+1.8VDC core logic PLL voltage check 

TP22 

+3.3VDC IC supply voltage check 

RJ-45 Ethernet Connector 

The RJ-45 Connector (J2) connects to standard CAT-5 Ethernet cable to interface with 10Base-
T/100Base-TX Ethernet devices. 

J2 also supports Auto-MDIX and Auto-Negotiation / Forced Modes. 

 

 

Содержание ADK-5200

Страница 1: ...QSG 5200 Rev A Holt Integrated Circuits ADK 5200 Quick Start Guide HI 5200 10Base T 100Base TX Physical Layer Transceiver April 2018 ...

Страница 2: ...QSG 5200 2 Holt Integrated Circuits REVISION HISTORY Revision Date Description of Change QSG 5200 Rev New 02 09 18 Initial Release Rev A 04 23 18 Remove HI 5201 option ...

Страница 3: ... reliable detection of and correction for crossover and straight through cables The device comes in a 32 pin lead free QFN package and provides an ideal solution for 10Base T 100Base TX applications that have limited PCB board space The HI 5200 ADK evaluation board ADK 5200 provides a convenient platform to evaluate HI 5200 features All device configuration pins are accessible either by jumpers te...

Страница 4: ...ard with Ethernet MACs that expose the MII interface Configuration of the HI 5200 is accomplished through on board jumper selections and or by PHY register access via the MDC MDIO management pins of the MII Interface Other features include a RJ 45 Jack for Fast Ethernet cable connection programmable LEDs for reporting link status and activity and a manual reset button for quick reboot after reconf...

Страница 5: ...llows upper layer devices to monitor and control the states of the HI 5200 An external device with MDC MDIO capability can read the PHY status or configure write the PHY registers The MIIM frame format and timing information can be found in the HI 5200 Datasheet and in Clause 22 of the IEEE 802 3 Specification The HI 5200 PHY board has a bottom side 50 pin connector J1 for MII connection Table 1 l...

Страница 6: ... management information via connector J1 in RMII mode In RMII mode the 50MHz clock from the MAC is connected to the XI pin The HI 5200 ADK PHY evaluation board and MAC hardware devices can be configured to RMII mode and interface with each other using the same J1 connector interface The board changes to support RMII mode are as follows 1 Remove crystal circuit Y1 C16 C17 and TXC clock termination ...

Страница 7: ...finition J1 Pin Signal J1 Pin Signal 1 2 3 4 5 5V 6 5V 7 MDIO 8 GND 9 MDC 10 GND 11 not used 12 GND 13 not used 14 GND 15 RXD1 16 GND 17 RXD0 18 GND 19 RXDV 20 GND 21 not used 22 GND 23 RXER 24 GND 25 not used 26 GND 27 REFCLK 28 GND 29 TXEN 30 GND 31 TXD0 32 GND 33 TXD1 34 GND 35 not used 36 GND 37 not used 38 GND 39 not used 40 GND 41 not used 42 GND ...

Страница 8: ...QSG 5200 8 Holt Integrated Circuits J1 Pin Signal J1 Pin Signal 43 5V 44 5V 45 46 47 48 49 50 ...

Страница 9: ...s and toggle the on board manual reset button S1 for the new setting s to take effect The HI 5200 ADK PHY evaluation board jumper settings are defined in Table 3 below Table 3 HI 5200PC Evaluation Board Jumper Definitions Jumper Definition Open default Closed JP1 PHYAD0 1 0 JP2 PHYAD1 0 1 JP3 PHYAD2 0 1 Jumper Definition CONFIG 2 0 Mode JP4 CONFIG0 open open open MII default JP5 CONFIG1 open open ...

Страница 10: ...2 0 100 PCS Loopback All other CONFIG 2 0 combinations are reserved JP7 20 ISO ISOLATE Mode Pull Up Enable Pull Down Disable default At power up reset the state of this pin is latched into register 0 bit 10 JP9 31 SPEED SPEED Mode Pull Up 100Mbps default Pull Down 10Mbps At power up reset the state of this pin is latched into register 0 bit 13 as the Speed Select and is also latched into register ...

Страница 11: ...t Description TP1 Interrupt Signal U1 pin 21 with external pull up TP2 Signal Ground TP3 Signal Ground TP20 5VDC input DC voltage check TP21 1 8VDC core logic PLL voltage check TP22 3 3VDC IC supply voltage check RJ 45 Ethernet Connector The RJ 45 Connector J2 connects to standard CAT 5 Ethernet cable to interface with 10Base T 100Base TX Ethernet devices J2 also supports Auto MDIX and Auto Negoti...

Страница 12: ...ned in the following table Table 6 Definitions for HI 5200PC PHY Evaluation Board LEDs LED Mode LED1 U1 pin 31 LED0 U1 pin 30 00 Speed U1 Pin 31 State LED State Link Activity U1 Pin 30 State LED State 10BT H OFF No Link H OFF 100BT L ON Link L ON Activity Toggle Blinking 01 Activity U1 Pin 31 State LED State Link U1 Pin 30 State LED State No Activity H OFF No Link H OFF Activity L ON Link L ON 10 ...

Страница 13: ...ACT ND Panasonic ERJ 6GEYJ102V 16 8 Resistor 4 7K 1 8W 5 0805 SMD R3 R18 R25 R30 P4 7KACT ND Panasonic ERJ 6GEYJ472V 17 1 Resistor 6 49K 1 8W 1 0805 SMD R15 P6 49KCCT ND Panasonic ERJ 6ENF6491V 18 2 Resistor 10K 1 8W 5 0805 SMD R1 R2 P10KACT ND Panasonic ERJ 6GEYJ103V 19 1 Diode Gen 100V 300mA SOD 123 D1 1N4148W FDICT ND Diode Inc 1N4148W 7 F 20 1 Ferrite Bead 31 Ohm 1206 SMD FB1 445 6170 1 ND TDK...

Страница 14: ...2 TD1 TD0 TXEN TXC TXER RXER RXCLK RXDV RXD0 RXD1 RXD2 RXD3 Place R19 close to J1 pin 12 DigiKey 399 3443 1 ND 1808 MOUNTED FAR SIDE AS SEEN FROM TOP X RAY VIEW 5V DC Power Input Power_ON Reset Pulse H1102 HOLT INTEGRATED CIRCUITS C8 10uF C8 10uF R28 4 7K R28 4 7K R21 33 R21 33 TP17 TP17 TP3 TP3 JP8 JUMPER JP8 JUMPER R10 49 9 R10 49 9 R11 49 9 R11 49 9 R1 100K R1 100K R32 1K R32 1K S1 SW PUSHBUTTO...

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