HOLT ADK-5200, Быстрый старт

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QSG-5200
10 Holt Integrated Circuits
Table 4 lists the pin strapping definitions for the HI-5200 ADK PHY evaluation board jumpers.
Table 4. HI-5200PC Pin Strapping Options on PHY Evaluation Board.
Jumper U1 Pin #
Pin
Name
Pin Function
JP3
JP2
JP1 15
14
13 PHYAD2
PHYAD1
PHYAD0
The PHY address is latched at power-up / reset
and is configurable to any value from 1 to 7.
The default PHY address is 00001.
PHY address bits [4:3] are always set to 00.
JP6
JP5
JP4 18
29
28 CONFIG2
CONFIG1
CONFIG0
The CONFIG[2:0] pins are latched at power-up / reset and
are defined as follows:
CONFIG[2:0] = 000 MII Mode (default)
CONFIG[2:0] = 001 RMII Mode
CONFIG[2:0] = 100 PCS Loopback
All other CONFIG[2:0] combinations are reserved.
JP7 20 ISO
ISOLATE Mode
Pull-Up = Enable
Pull-Down = Disable (default)
At power-up / reset, the state of this pin is latched into
register 0 bit 10.
JP9 31 SPEED
SPEED Mode
Pull-Up = 100Mbps (default)
Pull-Down = 10Mbps
At power-up / reset, the state of this pin is latched into
register 0 bit 13 as the Speed Select, and is also latched
into register 4 (Auto Negotiation Advertisement) as the
Speed capability support.
JP10 16 DUPLEX
DUPLEX Mode
Pull-Up = Half Duplex (default)
Pull-Down = Full Duplex
At power-up / reset, the state of this pin is latched into
register 0 bit 8 as the Duplex Mode.
JP8 30 NWAYEN
Nway Auto-Negotiation Enable
Pull-Up = Enable Auto-Negotiation (default)
Pull-Down = Disable Auto-Negotiation
At power-up / reset, the state of this pin is latched into
register 0 bit 12.