Hitachi MB-6890, Руководство по обслуживанию

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6-7
Keyboard
circuit
Figure
6-28 shows
the
general
structure
of
the keyboard.
1.
Input
of
HP
signal (scan
clock
:
Horizontal pulse
l5.75KHZ) to X-counter
(IClOl. IClO2)
startsthe count
and
output
of
the
count
down
is
inputted
to
decoder
(IC86).
By
this,
"L" output
of the
UECUUQP
scans.
2. By
input of the
carry
out singal (output Q
of
IC102) of X counter to
the B pin of
the
same
IC,
the count
down
of
Y counter
(IClO2) starts
then its
output
signal
is
inputted
to the
multiplexer (IC9O)
and its
reference points
scans.
3.
By
key input,
on
matrix (x, y)
for example (xo, yo)
is
ON,
multiplexer
output
Y
becomes L
when scanning position
xl
of the
i ‹ C O d E r
and the
reference point
yr
of the multiplexer
becomes
x1=x0
and
y1=y0.
4.
By
this,
output
of the counter stop
drive
switch circuit pin No.
5
as
H"leve1,
counter
will
stop
when
HP
signal
gate
(IC97)
is closed after
IRQ
interrupt. ~
5.
By
reading
allocated address
(SFFEO)
on
keyboard
which
was
done by MPU
IRQ
routine, keyboard
read signal (IC97 6 pin)
goes
"L", three state
buffer (IC98, IC88)
are
enabled,
then
the
state
(Keycode)
of the
X counter
and
Y
counter
are
read
to MPU.
After
this, keycode
in
MTU
is converted to
character code by software.
6. When
the
keyboard
read signal
goes
"H" after reading keycode
in
MPU
three
state
buffer becomes high
impedance,
IRQ
interrupt
is
released
then, X-counter
drive startsafter opening HP signal gate.
6-8 INTERFACES
6-8-l Cassette SAVE
load
circuit/RS
232C interface
circuit.
1.
Cassette
interface/RS-232C switching
circuit.
In cassette SAVE
load
circuit
and
RS-232C interface
circuit, ACIA (IC84)
is
commonly
used
as
data input/output IC.
This switching
is done by
RS/C
SW signal.
When the RS/C SW signal
which is inputted
1
pin
of IClll is
Low,
cassette
circuit is selected and if it
is’H1
RS-232C circuit is selected.
The table
6-14 shows the
relation
of RS/C signal
and IClll
output.
2. Clock generating
circuit
Because
different clock
frequency
is used in
cassette
and RS-232C, E
TTL
(Looe
MHZ; in
cassette
and 16.128
MHZ
in
Rszszc
dircuit is
divided in
each circuit.
This divide is
done by
binary counter (IC122,
ICl23, ICl24).
Table 6-14 shows the relationship between
RS/C
SW
signal and
each binary
counter output
clock frequency.
3. Cassette SAVE
circuit
Fig. 6-3O.shows
the
cassette SAVE
circuit and Fig. 6-31 shows
the input/
output
timing of
each
IC.
In cassette SAVE
circuit,
parallel
data signal from MPU
is converted
to
serial
data signal by ACIA
(K84) then further converted to FSK
(Frequency
shift
keying)
and
used
as
SAVE
signal
to
the cassette.
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