\
’k
a
simple
R/C
network
may
be
used
to
reset
the
entire
system.This
higher
threshold
voltage
ensures
that
all
peripherals
are
out
of
the
reset
state
before
the
Processor.
*HALT
A
Low
level
on
this
input
pin
will
cause
the
MPU
to
stop
running
at
the
end
of
the
present
instruction
and
remainhelted
indefinitely
without
loss
of
data.
When
halted,
the
BA
output
is
driven
High
indicat-
ing
the
buses
are
high
impedance.
BS
is
also
High
which
indicates
the
processor
is
in
the
Halt
or
Bus
Grant
state.
*HALT
A
Low
level
on
this
input
will
cause
the
MPU
to
stop
running
at
the
end
of
the
present
instruction
and
remain
halted
indefinitelywithout
loss
of
data.
When
halted,
the
BA
output
is
driven
High
indicating
the
buses
are
high
impedance.
BS
is
also
High
which
indicates
the
processor
is
in
the
Halt
or
Bus
Grant
State,
Bus
Available,
Bus
Status(BA,BS)
The
BA
output
is
an
indication
of
an
internal
control
signal
which
makes
the
MOS
buses
of
the
MPU
high
impedance.
This
signal
does
not
imply
that
the
bus
will
be
available
for
more
than
one
cycle.
when
BA
goes
Low,
an
additional
dead
cycle
will
elapse
before
the
MPU
acquires
the
bus.
The
BS
output
signal,
when
decoded
with
BA,
representing
the
MPU
state(valid
with
leading
edge
of
Q).
MPU
State
Definition
BA
|
as
MPU
stare
0
0
Normal
(Running)
0
1
Interrupt
or
RESET
Acknowledge
1
0
SYNC
Acknowledge
1
1
HALT
or
Bus
Grant
interrup
Acknowledge
is
th§_indicated
during
both
cycle
of
a
hardware
vector
fetch(RES,NMI,FIRQ,IRQ,SWI,SWI2,SWI3).
This
signal,
plus
decod-
ing
of
the
lower
four
address
lines,can
provide
the
user
with
an
indication
of
which
interru
t
level
‘
b
by
device.
Sync
Acknowledge
is
indicated
whi
synchronization
on
an
interrupt
line.
Halt/Bus
Grant
is
true
when
the
HD6809
is
in
a
Halt
or
Bus
Grant
condition.
p
is
eing
served
and
allow
vectoring
le
the
MPU
is
waiting
for
external
11
Содержание MB-6890
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