6-6
Video
Signal
Generator
Block
Video
Signal
Generator
Block
is
shown
at
fig
6-21.
The
explanation
of
each
circuit
is
as
below.
6-6-1
Character
Generator
Circuit
Fig
6-22
shows
the
character
generator
circuit.
In
character
generator
circuit,
the
change
of
the
output
character
to
data
bit
is
required
according
to
the
interlace
mode
or
non
interlace
mode
per
dots
structure
of
each
character.
Colour
RAM
output,
G/C signal
is
inputted
to
IClO7
20
pin
(chip
select
terminal)
When
G/C
signal
is
Low,
i.e.
when
it
is
character
mode,
character
generator
ROM
IClO7
becomes
operable.
IClO7
consists
of
4K
Byteg
raster
address
signal
RAA
-RAA
and
display
RAM
data
bit
DDO-DD7
is
inputted
to
address
input
AO-A
and
characger
is
outputted
according
to
two
scanning
modes
(interlace
mode
and
non-interlace
mode).
Fig
6-23
character
generator
ROM
can
be
divided
into
three
3f93S
b55iC3llY5
1)
Uses
16
byte
per
one
character
and
used
for
interlace
pattern
recording
ifea.
.
3)
one
character
pattern.
2)
Uses
8
Byte
per
character
and
used
for
Non-Interlace
pattern
recording.
Is
interlace
Non-Interlace
common
area
and
have
record
of
8
Bytes
per
In
this
case,
if
non-interlace
mode,
only
2)
and
3)
area
are
in
use,
further
more,
if
character
display
is
required
which
is
recorded
in
3)
area,
the
same
pattern
in
th
field
and
even
field
is
read
each
other
and
make
the
balance
with
the
character
pattern
in
area
l)
by
making
double
dots
number
of
16
to
vertical
direction.
Therefore,
the
complicatedpattern
of
128
varieties
are
recorded
in
area
1).
6-6-2
Graphic
generator
circuit
Graphic
is
divided
into
high
resolution
mode
and
regular
mode.
This
mode
selection
is
done
by
the
HRSO-SW
signal
which
is
outputted
MODE
SEL
register
IC39
2
pin.
Fig.
6-24
shows
graphic
generator
circuit.
In
fig.
6-24,
HRSO-SW
signal
is
connected
to
ICll3,
ICll4
If
HRSO
SW=H,high
resolution
mode
is
obtained
and
if
Low,
In
high
resolution
mode,
A
side
input
which
is
the
output
ICll3,
ICl14
output
and
B
side
input
is
connected
in
case
,
1
it
-5
UL
of
pin
(select
terminal).
becomes
regular
mode.
ICll2
is
connected
to
regular
mode.
In
regular
mode,
raster
address
signal
of
RAA3,
RAA2
are
inputted
to
ICll2
select
input
2,
14
pin.
By
this
signal,
data
bit
DD
-DD7
is
switch
outputted,
one
character
area
is
divided
by
8
as
shown
fig.
2-25
(a).
On
the
other
hand,
in
high
resolution
mode,
data
bit
DD
-DD
is
outputted
as
it
is,
l
character
area
is
divided
by
64
as
shown
fig.
6-29
(by.
This
is
because
raster
address
direction
is
divided
8
by
raster
address
RAA3-RAA1
in
one
character
area
using
address
switch
circuit.
The
dividend
is
done
l
character
area
unit
in
fig.
6-25,
double
resolution
of
that
of
40
character
mode
to
horizontal
direction
is
obtained
in
case
of
80
character
mode
if
we
compare
the
relationship
between
display
mode
and
graphic
resolution
ratio
is
as
per
table
6-13.
6-6-3
Video
Signal
generator
circuit
Video
signal
Synchronous
signal
generator
circuit
is
in
Fig.
6-26.
-
(1)
8
bit
signal,
which
is
made
in
character
generator
or
graphic
generator
circuit,
is
converted
to
serial
SiQD5l
by
ICll7
to
make
the
brightness
signal
in
video
/
e
odd
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