Description and Requirements
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NXIO 100-RE Board | Configuration and Hardware Description
DOC061101UM02EN | Revision 2 | English | 2011-06 | Released | Public
Hilscher, 2006-2011
The data switch interconnects the ARM CPU, communication and Host
controllers, memory blocks and peripheral units via five data paths. This
allows the controllers to transmit their data in parallel, contrary to the
traditional sequential architecture with only one common data bus and
additional bus arbitration cycles.
The controllers of the four communication channels are structured on two
levels and are identical to each other. They consist of dedicated Alas and
special logic units that receive their protocol functions via microcode,
combining the performance of dedicated (single-) protocol controllers with
the flexibility of a CPU. Two of these channels can further be linked to
integrated PHs for Ethernet communication.
The Medium-Access-Controller xMAC sends or receives the serial data
stream according to the respective bus access process and encrypts or
converts these into Bytes.
The Protocol Execution Controller xPEC compiles these into data packets
and controls the telegram traffic, accomplished by DMA transfers. In
addition, every channel has a dual-port-memory available for status
information or as local data image.
By its intelligent communication ALUs, the netX can implement the most
varied protocols and protocol combinations and can synchronize them
independently of the CPU response time – an absolutely new feature in
industrial communication technology.
