I2S_0_CLOCK
DVO_CLK_P
DVO_D7
DVO_D5
DVO_D6
DVO_D3
DVO_D4
DVO_D0
DVO_D2
E BI_~TS
EBI_~DS
EBI_~TSIZE1
AU D0_SPDIF
U SB0_PWRON
EBI_R~W
EBI_A25
I2S_0_DATA1
I2S_0_DATA0
I2S_0_DATA2
EBI_~WE0
EBI_~WE1
I2S_0_DATA3
I2S_0_LR
+2V5_BCM7440
I2S_S_DATA
DVO_D1
E BI_~TSIZE0
EBI_~RD
U SB1_PWRON
GND
GND
GND
GND
GND
GND
GND
GND
GND
+3V3
+3V3
+1V8
+1V2
EBI_~RD
EBI_~WE1
EBI_~DS
DVO_D0
EBI _~TS
DVO_D2
DVO_D1
DVO_D4
DVO_D3
DVO_D6
DVO_CLK_P
DVO_D5
DVO_D7
+2V5_BCM7440
I2S_0_CLOCK
I2S_0_LR
AUD0_SPDIF
I 2S_0_DATA0
I 2S_0_DATA1
I 2S_0_DATA2
I2 S_0_DATA3
EBI_R~W
EBI_A25
USB0_PWRON
EBI_~TSIZE1
E BI_~TSIZE0
EBI_~W E0
I2S _S_DATA
USB1_PWRON
3: DDR2 Controller Manual Initialization
2: DDR2 bank 0 size = 256/512 MB
1: DDR2 bank 0 size = 128 MB
0: DDR2 bank 0 size = 64 MB
strap_ebi_boot_memory
1
(CLUSTER)
SOC
(CLUSTER)
1- Note these configuration resistors do not need to be close to the BCM7440. So, place them at the destination of the trace.
It will clear the BCM7440 area and help the chip layout.
Boot strap option --> Design notes and Layout Guidelines:
strap_ebi_invert_addr
strap_nand_flash
strap_NMI_polarity
strap_ebi_cs_swap
strap_reset_ext_mode
strap_test_debug_en_1
strap_test_debug_en_0
strap_ddr2_0_size_1
strap_ddr2_0_size_0
strap_ddr2_1_size_1
strap_ddr2_1_size_0
strap_ddr2_mhz_1
strap_ddr2_mhz_0
strap_system_big_endian
strap_pci_client
strap_pci_memwin1_en
strap_pci_memwin2_en
strap_pci_memwin_size_0
strap_pci_memwin_size_1
strap_reset_outb_def_value
strap_xtal_adj3
strap_xtal_adj2
strap_xtal_adj1
strap_xtal_adj0
strap_ebi_rom_size1
strap_ebi_rom_size0
strap_33_27_MHZ_clock
0
0
0
0
strap_nand_flash
strap_NMI_polarity
strap_ebi_cs_swap
strap_reset_ext_mode
strap_test_debug_en_1
strap_ddr2_0_size_1
strap_ddr2_0_size_0
strap_ddr2_1_size_1
strap_ddr2_1_size_0
strap_test_debug_en_0
strap_ddr2_mhz_1
strap_ddr2_mhz_0
strap_spi_slave_enable
strap_ebi_boot_memory
strap_system_big_endian
strap_pci_client
strap_pci_memwin1_en
strap_pci_memwin2_en
strap_pci_memwin_size_1
strap_pci_memwin_size_0
strap_33_27_MHZ_clock
strap_reset_outb_def_value
strap_xtal_adj3
strap_xtal_adj2
strap_xtal_adj1
strap_xtal_adj0
Adjust the 54MHz oscillator bias current
strap_ebi_rom_size1
strap_ebi_rom_size0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
Boot Strap Options
1
0
1
under chip.
BCM7440 Power
BOOTSTRAP
1
0
1: Invert upper bits of EBI address
0: Do not invert EBI address
1: External NAND FLASH present
0: External NOR FLASH present
1: High-active interrupt
0: Low-active interrupt
1: Swap CS_0 and CS_1 signals
0: No swap
strap_ebi_invert_addr
0: DDR2 bank 0 size = 64 MB
1: DDR2 bank 0 size = 128 MB
2: DDR2 bank 0 size = 256/512 MB
3: DDR2 Controller Manual Initialization
0: DDR2 Banks = 200/400 MHZ
1: DDR2 Banks = 266/533 MHZ
2: DDR2 Banks = 333/667 MHZ
3: DDR2 Banks = 400/800 MHZ
1: SPI slave port configured
0: BSC slave port configured
0: Boot Flash = 8 bits
1: Boot Flash = 16 bits
0: System is little endian
1: System is big endian
1: PCI in client (slave) mode
0: PCI in bridge (master) mode
0: PCI memwin 1 disable
1: PCI memwin 1 enable
0: PCI memwin 2 disable
1: PCI memwin 2 enable
2: 128 MByte window
1: 64 MByte window
3: 256 MByte window
0: 32 MByte window
1: 33 MHz clock output
0: 27 MHz clock output
1: NOR: 16 MBytes NAND: Ebable ECC
0: NOR 64 MBytes NAND: Ebable ECC
2: NOR: 8 MBytes NAND: Disable ECC
3: NOR: 4 MBytes NAND: Disable ECC
int Fix.
Place 4.7uF directly
0
2008.5.19
1.5K
R514
100MW
1%
2
1
22UF
C56
1
2
1.5K
R39
100MW
1%
2
1
0.1UF
C612
1
2
0.1UF
C628
1
2
0.1UF
C34
1
2
0.1UF
C629
1
2
47UF
C581
1
2
0.1UF
C660
1
2
1.5K
R29
100MW
1%
2
1
4.64K
R63
100MW
1%
2
1
4.64K
R516
100MW
1%
DEPOP
2
1
22UF
C534
1
2
0.1UF
C541
1
2
1.5K
R65
100MW
1%
2
1
22UF
C672
1
2
0.1UF
C583
1
2
0.1UF
C646
1
2
0.1UF
C648
1
2
0.1UF
C69
1
2
1.5K
R28
100MW
1%
2
1
4.64K
R518
100MW
1%
DEPOP
2
1
22UF
C613
1
2
0.1UF
C57
1
2
1.5K
R38
100MW
1%
2
1
22UF
C50
1
2
0.1UF
C574
1
2
0.1UF
C584
1
2
4.64K
R519
100MW
1%
2
1
4.64K
R61
100MW
1%
2
1
0.1UF
C51
1
2
1.5K
R66
100MW
1%
2
1
4.7UF
C619
1
2
22UF
C36
1
2
4.64K
R523
100MW
1%
2
1
0.1UF
C43
1
2
0.1UF
C625
1
2
22UF
C627
1
2
1.5K
R520
100MW
1%
2
1
0.1UF
C42
1
2
0.1UF
C54
1
2
1.5K
R36
100MW
1%
2
1
4.7UF
C620
1
2
0.1UF
C641
1
2
4.64K
R517
100MW
1%
2
1
0.1UF
C572
1
2
1.5K
R67
100MW
1%
2
1
0.1UF
C615
1
2
4.7UF
C623
1
2
10UF/10V
C616
1
2
0.1UF
C58
1
2
4.64K
R521
100MW
1%
2
1
4.7UF
C618
1
2
1.5K
R515
100MW
1%
2
1
0.1UF
C606
1
2
0.1UF
C611
1
2
1.5K
R30
100MW
1%
2
1
0.1UF
C621
1
2
0.1UF
C53
1
2
4.64K
R525
100MW
1%
2
1
22UF
C671
1
2
0.1UF
C614
1
2
0.1UF
C636
1
2
1.5K
R522
100MW
1%
DEPOP
2
1
4.64K
R60
100MW
1%
2
1
0.1UF
C588
1
2
0.1UF
C65
1
2
1.5K
R62
100MW
1%
2
1
1.5K
R541
100MW
1%
2
1
0.1UF
C610
1
2
0.1UF
C525
1
2
0.1UF
C33
1
2
0.1UF
C587
1
2
22UF
C66
1
2
0.1UF
C70
1
2
1.5K
R34
100MW
1%
2
1
22UF
C68
1
2
0.1UF
C585
1
2
0.1UF
C55
1
2
4.64K
R64
100MW
1%
2
1
22UF
C67
1
2
4.64K
R529
100MW
1%
2
1
22UF
C52
1
2
0.1UF
C647
1
2
1.5K
R40
100MW
1%
2
1
4.64K
R32
100MW
1%
DEPOP
2
1
22UF
C35
1
2
0.1UF
C586
1
2
0.1UF
C661
1
2
4.64K
R59
100MW
1%
2
1
4.64K
R524
100MW
1%
2
1
47UF
C547
1
2
0.1UF
C617
1
2
Main Board Electric Diagram: BOOT STRAP OPTIONS & BCM7440B
48
harman/kardon
BDP 1 / BDP 10 Service Manual
Содержание BDP 1/120
Страница 32: ...Front Board Print layout Top side 32 harman kardon BDP 1 BDP 10 Service Manual...
Страница 33: ...Front Board Print layout Bottom side 33 harman kardon BDP 1 BDP 10 Service Manual...
Страница 34: ...IR Board Print layout Bottom side 34 harman kardon BDP 1 BDP 10 Service Manual...
Страница 35: ...Power Board Print layout Bottom side 35 harman kardon BDP 1 BDP 10 Service Manual...
Страница 36: ...Main Board Print layout Top side 7 20 36 harman kardon BDP 1 BDP 10 Service Manual...
Страница 37: ...Main Board Print layout Bottom side 37 harman kardon BDP 1 BDP 10 Service Manual...