3 Development Board Circuit
3.5 DDR3
DBUG385-1.1E
12(23)
Figure 3-4 Connection Diagram of FPGA and DDR3
DDR3_BA[2..0]
DDR3_A[13..0]
DDR3 SDRAM
2Gbit
DDR3_DQ[15..0]
DDR3_UDQSn
DDR3_LDQSn
DDR3_UDQSp
DDR3_LDQSp
DDR3_UDM
DDR3_LDM
DDR3_CASn
DDR3_RASn
DDR3_WEn
DDR3_ODT
DDR3_CK_EN
DDR3_CSn
DDR3_RSTn
DDR3_CKn
DDR3_CKp
3.5.2
Pinout
Table 3-3 DDR3 Pinout
Signal Name
FPGA Pin No. BANK
I/O
Description
DDR3_A0
F7
6
1.5V
Address
DDR3_A1
A4
5
1.5V
Address
DDR3_A2
D6
5
1.5V
Address
DDR3_A3
F8
6
1.5V
Address
DDR3_A4
C4
6
1.5V
Address
DDR3_A5
E6
6
1.5V
Address
DDR3_A6
B1
5
1.5V
Address
DDR3_A7
D8
6
1.5V
Address
DDR3_A8
A5
5
1.5V
Address
DDR3_A9
F9
6
1.5V
Address
DDR3_A10
K3
4
1.5V
Address
DDR3_A11
B7
6
1.5V
Address
DDR3_A12
A3
5
1.5V
Address
DDR3_A13
C8
6
1.5V
Address
DDR3_BA0
H4
5
1.5V
Bank address
DDR3_BA1
D3
5
1.5V
Bank address
DDR3_BA2
H5
4
1.5V
Bank address
DDR3_CASn
R6
4
1.5V
Column address
Содержание DK_START_GW2A-LV18PG256C8I7_V2.0
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