3 Development Board Circuit
3.3 Power Supply
DBUG385-1.1E
9(23)
Figure 3-1 Connection Diagram of FPGA Download and Configuration
FLASH_SPI_MISO
FLASH_SPI_MOSI
FLASH_SPI_CS_N
FLASH_SPI_CLK
P10
R10 M9 L10
JTAG_TCK
JTAG_TDO
JTAG_TDI
JTAG_TMS
USB-to-
JTAG Chip
USB_D+
USB_D-
C6
A7
A6
B8
Configuration
FLASH
3.2.2
Pinsout
Table 3-1 FPGA Download and Pinout
Signal Name
FPGA Pin No. BANK I/O
Description
JTAG_TCK
A7
2
3.3V JTAG Signal
JTAG_TDO
C6
2
3.3V JTAG Signal
JTAG_TDI
A6
2
3.3V JTAG Signal
JTAG_TMS
B8
2
3.3V JTAG Signal
FLASH_SPI_MISO
P10
3
3.3V FLASH signal configuration
FLASH_SPI_MOSI
R10
3
3.3V FLASH signal configuration
FLASH_SPI_CS_N
M9
3
3.3V FLASH signal configuration
FLASH_SPI_CLK
L10
3
3.3V FLASH signal configuration
3.3
Power Supply
3.3.1
Introduction
5V power (Input: 100-240V~50/60MHz 0.5A, output: DC +5V 2A) The
development board generates 3.3V, 2.5V, 1.5V, 1.2V, 1.0V, and 0.75V
(required by DDR3).
One redundant power location is reserved on the development board.
A LDO can be wielded to generate 3.3V, 1.5V, and 1.0V. The rated current
is 2A. When the redundant power is used to replace the main power, you
need to take off the main power's magnetic beads to avoid the power
conflicts.
Содержание DK_START_GW2A-LV18PG256C8I7_V2.0
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