can only access memory up to 16MB.
P2C/C2P Concurrency
When Disabled, CPU bus will be occupied during the entire PCI opera-
tion period.
System BIOS Cacheable
Allows the system BIOS to be cached for faster system performance.
Video RAM Cacheable
This item allows you to "Enabled" or "Disabled" on Video RAM Cache-
able.
Frame Buffer Size
This item defines the amount of system memory that will be shared and
uses as video memory.
AGP Aperture Size
Options : 4, 8, 16, 32, 64, 128, 256
This option selects the size of the AGP aperture. The aperture is aportion
of the PCI memory address range dedicated as graphics memo- ry
address space. Host cycles that hit the aperture range are forwarded to
the AGP without need for translation. This size also determines the
maximum amount of system RAM that can be allocated to the graphics
card for texture storage.
AGP Aperture size is set by the formula : maximum usable AGP memo- ry
size x 2 plus 12MB. That means that usable AGP memory size is less
than half of the AGP aperture size. That's because the system needs AGP
memory (uncached) plus an equal amount of write combined memory area
and an additional 12MB for virtual addressing. This is address space, not
physical memory used. The physical memory is allocated and released as
needed only when Direct3D makes a "create non-local surface" call.
AGP-4X Mode
Set to Enabled if your AGP card supports the 4X mode, which transfers
video data at 1066MB/s.
AGP Driving Control
This item is use for control AGP drive strength.
Auto: Setup AGP drive strength by default setting.
Manual: Setup AGP drive strength by manual setting.
AGP Fast Write
To enable this function can increase VGA performance on graphic
designed.
OnChip Sound
This menu can access the sound controller automaticlly
CPU to PCI Write Buffer
This controls the CPU write buffer to the PCI bus. If this buffer is
disabled, the CPU writes directly to the PCI bus. Although this may seem
like the faster and thus, the better method, this isn't true. Because the
CPU bus is faster than the PCI bus, any CPU writes to the PCI bus has
to wait until the PCI bus is ready to receive data. This prevents the CPU
from doing anything else until it has completed sending the data to the
PCI bus. Enabling the buffer enables the CPU to immediately write up to
4 words of data to the buffer so that it can continue on another task
without waiting for those 4 words of data to reach the PCI bus. The data
in the write buffer will be written to the PCI bus when the next PCI bus
read cycle starts. The difference here is that it does so without stalling
the CPU for the entire CPU to PCI transaction. Therefore, it's
recommended that you enable the CPU to PCI write buffer.
PCI Dynamic Bursting
When enabled, data transfer on the PCI bus, where possible, make use
of the high-performance PCI bust protocol, in which greater amounts of
data are transferred at a single command.
PCI Master 0 WS Write
This function determines whether there's a delay before any writes to
the PCI bus. If this is enabled, then writes to the PCI bus are executed
immediately (with zero wait states), as soon as the PCI bus is ready to
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