Glenayre GL-T8541, Руководство пользователя, Страница: 30 / 90

GL-T8541 PA Glenayre Document Number: 9110.01002
THEORY OF OPERATION 09/10/99
Page: 6-4 Copyright © 1997 Glenayre
6.3 The 1 to 3 Splitter Board
The right side of Figure 6-2 shows a block diagram of the 1 to 3 splitter board. Refer to
Figure 6-14 and Figure 6-15 for detailed circuit board assembly and schematic diagrams.
The three outputs of this splitter are in phase, with each delivering 6 watts to its respective
power amplifier board. The 1 to 3 splitter consists of two Wilkinson hybrid splitters, Hy1
and Hy2. Hy1 is an unbalanced splitter with two thirds of the input power going to hy2 and
one third going to one of the three output terminal of the 1 to 3 splitter board. The line
connecting the low power side of Hy1 to its output is long enough to introduce additional
delay to its output and cause it to be in phase with the outputs of Hy2. Hy2 divides its input
power evenly between its two outputs; therefore equal RF power levels are delivered from
all outputs of the 1 to 3 splitter.
6.4 PA Board
Refer to Figure 6-3 for a simplified block diagram of the 120 watt power amplifier board.
Refer to Figure 6-16 and Figure 6-17 for detailed circuit board assembly and schematic
diagrams. The GL-T8541 transmitter uses three PA boards to achieve rated transmitter
output.
The 120 watt PA board consists of two FETs in push pull configuration. The push pull
signal required by the input of each FET is obtained through the use of coaxial transformer
L7. The coaxial line functions as an unbalanced to balanced transformer. Two ferrite beads
are positioned around the coaxial to insure a balanced output signal with equal amplitudes
from the center conductor and shield of the line.
Microstrip techniques augmented with chip capacitors match the RF input and output
signals to the FETs.
The outputs of the two push pull FETs are combined into a single signal by the output
coaxial transformer L8. This coaxial transformer functions the same as the input
transformer.
The bias, idle current, gain, and output power of each transistor on the PA board, and
therefore the total output power of the PA board, is determined by the AGC voltage level
applied to the power amplifier board. The exact value of AGC voltage applied to the gates
of the PA board FETs can be adjusted at the PA board by potentiometer R7. Any noise or
RF signals are decoupled from the AGC signal by a resistor-capacitor-inductor filter
network in the PA board gate bias circuit. This network consists of resistors R3, R4, R8,
and R9 (shown on the block diagram); as well as C12, C13, C16, and C17 (shown on the
schematic). The positive limit of the AGC voltage, as well as protection from positive tran-
sients, is provided by zener diode CR1.
The AGC voltage is developed in the metering board as a result of a comparison of a dc
sample from the PA module RF output signal to a reference dc voltage supplied from the
DSP exciter. The lower limit of the AGC voltage is approximately -13 Vdc, and the positive
limit is approxi6 Vdc. When the transmitter is unkeyed, the AGC voltage is at the
-13 volt limit, preventing any conduction of the PA transistors. When the transmitter is
keyed and producing RF, the AGC voltage is between zero and 6 Vdc. In operation, the
AGC voltage should never reach the 6 Vdc limit.