BIOS Setup
- 100 -
Parameter
Description
NBIO RAS Common Options
Press [Enter] for more options.
NBIO RAS Global Control
– Options available: Manual/Auto. Default option is
Auto
.
NBIO RAS Control
– 0 = Disabled, 1 = MCA, 2 = Legacy.
– Options available: Disabled/MCA/Legacy. Default option is
MCA
.
Egress Poison Severity High
– Enter a value. Each bit set to 1 enables high severity on the
associated IOHC egress port. A bit of 0 indicates low severity.
Egress Poison Severity Low
– Enter a value. Each bit set to 1 enables high severity on the
associated IOHC egress port. A bit of 0 indicates low severity.
NBIO SyncFlood Generation
– This value may be used to mask SyncFlood caused by NBIO RAS
options. When set to TRUE SyncFlood from NBIO is masked.
When set to FALSE NBIO is capable of generating SyncFlood.
– Options available: Enabled/Disabled/Auto. Default option is
Auto
.
NBIO SyncFlood Reporting
– This value may be used to enable SyncFlood reporting to APML.
When set to TRUE SyncFlood will be reported to APML. When set
to FALSE that reporting will be disabled.
– Options available: Enabled/Disabled. Default option is
Disabled
.
Egress Poison Mask High
– Enter a value. These set the enable mask for masking of errors
logged in EGRESS_POISON_STATUS. For each bit set to 1,
errors are masked. For each bit set to 0, errors trigger response
actions.
Egress Poison Mask Low
– Enter a value. These set the enable mask for masking of errors
logged in EGRESS_POISON_STATUS. For each bit set to 1,
errors are masked. For each bit set to 0, errors trigger response
actions.
Uncorrected Converted to Poison Enable Mask High
– Enter a value. These set the enable mask for masking of
uncorrectable parity errors on internal arrays. For each bit set to
1, a system fatal error event is triggered for UCP errors on arrays
associated with that egress port. For each bit set to 0, errors are
masked.
Uncorrected Converted to Poison Enable Mask Low
– Enter a value. These set the enable mask for masking of
uncorrectable parity errors on internal arrays. For each bit set to
1, a system fatal error event is triggered for UCP errors on arrays
associated with that egress port. For each bit set to 0, errors are
masked.
Содержание R282-Z94
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Страница 16: ... 16 Hardware Installation 1 3 System Block Diagram ...
Страница 35: ... 35 System Hardware Installation 2 2 2 2 3 3 ...
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Страница 43: ... 43 System Hardware Installation Onboard SATA Cable NVMe Card Power Cable 3 12 Cable Routing ...
Страница 44: ...System Hardware Installation 44 CNV3022 CNV3132 NMVe Card 0 3 Cable NMVe Card 4 5 Cable CNV3134 ...
Страница 45: ... 45 System Hardware Installation CNV9134 NMVe Card 6 7 Cable NMVe Card 8 11 Cable CNV3022 CNV3132 ...
Страница 46: ...System Hardware Installation 46 CNV3132 NMVe Card 12 15 Cable NMVe Card 16 17 Cable CNV3134 ...
Страница 47: ... 47 System Hardware Installation CNV3132 CNV3022 NMVe Card 18 19 Cable Onboard NMVe Cable 20 21 Cable ...
Страница 48: ...System Hardware Installation 48 CNVP143 NMVe Card 22 23 Cable Rear HDD Backplane Board Power Cable ...
Страница 49: ... 49 System Hardware Installation Rear HDD Backplane Board Signal Cable HDD Backplane Board Power Cable ...
Страница 50: ...System Hardware Installation 50 HDD Backplane Board Signal Cable Front Panel USB 3 0 Ports Cable ...
Страница 51: ... 51 System Hardware Installation Front Panel LEDs and Buttons Cable ...
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Страница 56: ...Motherboard Components 56 This page left intentionally blankThis ...
Страница 73: ... 73 BIOS Setup 5 2 8 PCI Subsystem Settings ...
Страница 78: ...BIOS Setup 78 5 2 11 SATA Configuration ...
Страница 83: ... 83 BIOS Setup 5 2 16 Intel R I350 Gigabit Network Connection ...
Страница 85: ... 85 BIOS Setup 5 2 17 VLAN Configuration ...