Giga-tronics 8501A, Руководство по эксплуатации и техническому обслуживанию

Страница: 135 / 262

The CPU (Central Processing Unit) PC board controls all of the functions of the instrument. The CPU is
logically divided between those circuits shown on Sheet 1 of DWG# 16879 and those shown on Sheet 2
of DWG# 16879.
Sheet 1 of DWG# 16879 shows the following CPU functions:
•
The Microprocessor (MPU)
•
Address Decoding and Handshake
•
Unbuffered Memory
•
Reset Timer
•
Interrupt Priority Decoder
•
Data Buffers
Sheet 2 of DWG# 16879 shows the following CPU functions:
•
External Memory
•
Real Time Clock
•
Backup Battery circuit
Starting with Sheet 1 of DWG# 16879 and going in the same sequence as shown above, the functional
operation of each CPU sub-circuit is described as follows:
The Microprocessor
The Microprocessor is a Motorola 68000 MPU. It has a 16-bit data bus, 32-bit internal registers, and runs
on a 6-MHz clock frequency. If you need to see the timing of the MPU in its various modes of operation,
it is recommended that you refer to the manufacturer’s manual.
Address Decoding and Handshake
This circuit performs the address decoding for the memories and other devices included on the CPU
board and elsewhere in the instrument. It generates the device select signals for the various components,
creates the proper timing for each device, and performs the necessary handshaking for the transfer of data
between the CPU and the different devices.
U18A & B, U20B, and U19C decode address lines 20 through 23 to select the multiplexer U34. The
address strobe AS is active when the address lines hold a valid address.
Address lines 16, 17, 18, and 19 select one of the 16 outputs of the multiplexer, which will be used as the
device select line (CS0 through CS15). CS0 through CS7 address the memories; CS8 through CS13
address different I/O devices; and CS15 addresses devices that require a handshake according to the 6800
protocol.
U15A, U38, U19A, D & E, and U16 create the proper timing and handshaking for each device category.
When selecting one of the memories, U15A will produce a direct DTACK (Data Transfer ACKnowlege)
signal to U12 through NAND gate U21C. The MPU will then execute the data transfer without
introducing any additional wait states. When selecting one of the I/O devices (CS8 through CS13), the
output of U38D goes high thus enabling the shift register, U16, which is clocked by the 6 MHz system
clock. After three clock pulses, output QC goes high creating an active CE signal that is used by the
Analog PC board circuitry. After another clock pulse QD goes high, is inverted in U19A, and creates a
delayed DTACK through U21C. The MPU responds by inserting a corresponding number of wait states in
the data transfer which allows the device to time the data transfer. DTACK can also be received from any
external device connected to the CPU bus that has its own address decoding circuits.
When CS14 or CS15 are selected, U19E will generate a VPA (Valid Peripheral Address) signal through
NAND gate U21B. This tells the MPU that a valid 6800 device has been addressed, and the MPU will
respond by generating a data transfer according to the 6800 protocol. The E and VMA (Valid Memory
Theory of Operation
Manual No. 20790, Rev C, November 1998
4-9