Gibson MM516, Руководство пользователя

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MM516
User's Manual
26
Revision 1.4 7-8-2011
Hardware Description Manual
5.2.9 USB v2.0 Compliance
BlueCore 5 chip is qualified to USB Specification v2.0, details of which are available from http://www.usb.org.
The specification contains valuable information on aspects such as PCB track impedance, supply inrush current and
product labeling.
Although BlueCore 5 chip meets the USB specification, CSR cannot guarantee that an application circuit
designed around the chip is USB compliant. The choice of application circuit, component choice and PCB layout all
affect USB signal quality and electrical characteristics. The information in this document is intended as a guide and
should be read in association with the USB specification, with particular attention being given to Chapter 7.
Independent USB qualification must be sought before an application is deemed USB compliant and can bear the
USB logo. Such qualification can be obtained from a USB plugfest or from an independent USB test house.
Terminals USB_DP and USB_DN adhere to the USB Specification v2.0 (Chapter 7) electrical requirements.
5.2.10 USB 2.0 Compatibility
BlueCore 5 chip is compatible with USB v2.0 host controllers; under these circumstances the two ends agree
the mutually acceptable rate of 12Mbits/s according to the USB v2.0 specification.
5.3 Serial Peripheral Interface
BlueCore 5 chip uses 16-bit data and 16-bit address serial peripheral interface, where transactions may occur
when the internal processor is running or is stopped. This section details the considerations required when interfacing
to BlueCore 5 chip via the four dedicated serial peripheral interface terminals. Data may be written or read one
word at a time or the auto increment feature may be used to access blocks.
5.3.1 Instruction Cycle
The BlueCore 5 chip is the slave and receives commands on SPI_MOSI and outputs data on SPI_MISO. Table 4
shows the instruction cycle for an SPI transaction.
Table 4 Instruction Cycle for an SPI Transaction
With the exception of reset,SPI_CSB must be held low during the transaction. Data on SPI_MOSI is clocked into the
BlueCore 5 chip on the rising edge of the clock line SPI_CLK. When reading, BlueCore 5 chip will reply to
the master on SPI_MISO with the data changing on the falling edge of the SPI_CLK. The master provides the clock
on SPI_CLK. The transaction is terminated by taking SPI_CSB high.
Sending a command word and the address of a register for every time it is to be read or written is a significant
overhead, especially when large amounts of data are to be transferred. To overcome this BlueCore 5 chip offers
increased data transfer efficiency via an auto increment operation. To invoke auto increment, SPI_CSB is kept low,
which auto increments the address, while providing an extra 16 clock cycles for each extra word to be written or
read.