Genesys GEN10-330, Руководство пользователя, Страница: 68 / 82

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Refer to Tables 7-9 to 7-12 for details of the Enable and Event registers.
The Fault Enable Register is set to the enable faults SRQs.
1.Fault Enable Register
2.Fault Event Register
The Fault Event will set a bit if a condition occurs and it is enabled. The register is cleared when
FEVE?, CLS or RST commands are received.
Table 7-9: Fault Enable Register
BIT
Enable
bit name
Fault symbol
0 (LSB)
1
2
3
4
5
6
7(MSB)
Spare bit
AC Fail
Over Temperature
Foldback
Over Voltage
Shut Off
Output Off
Enable
SPARE
AC
OTP
FOLD
OVP
SO
OFF
ENA
Bit Set condition
Bit reset condition
User command:
"FENA nn" where
nn is hexadecimal
User command: "FENA nn"
where nn is hexadecimal (if
nn="00", no fault SRQs will
be generated).
Table 7-10: Fault Event Register
0 (LSB)
1
2
3
4
5
6
7(MSB)
Spare bit
AC Fail
Over Temperature
Foldback
Over Voltage
Shut Off
Output Off
Enable
SPARE
AC
OTP
FOLD
OVP
SO
OFF
ENA
Entire Event Register is
cleared when user sends
"FEVE?" command to read
the register.
"CLS" and power-up also
clear the Fault Event
Register. (The Fault Event
Register is not cleared by
RST)
BIT
Event
bit name
Fault symbol
Bit Set condition
Bit reset condition
Fault condition
occurs and it is
enabled.
The fault can set
a bit, but when
the fault clears
the bit remains
set.
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