PCI-SIO4 User Manual
General Standards Corporation
8302A Whitesburg Drive Huntsville, AL 35802, Phone: (256) 880-8787
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4.3
PCI DMA
The PCI DMA functionality allows data to be transferred to/from host memory from/to the SIO4’s onboard
FIFO buffers with the least amount of CPU overhead. The PLX Technology PCI9080 interface chip used
on the SIO4 cards handles all PCI DMA functions.
Due to the lack of interrupt sources needed by some device drivers, demand mode DMA transfers are not
fully supported by the SIO4 at this time.
4.4
ZILOG Z16C30 DMA
While not a “true” DMA in the technical sense, the Zilog DMA function does provide a means for data
transfer, mostly transparent to the user, to/from the Z16C30 serial controller chips from/to the SIO4’s
onboard FIFO buffers.
While in transmit mode, the Zilog DMA provides a mechanism by which each byte transferred to the
SIO4’s onboard transmit FIFO buffer, will automatically be read out by the Z16C30 chip and sent out to the
cable. This operation will continue as long as the transmit FIFO buffer has data in it.
While in receive mode, the Zilog DMA provides a mechanism by which each byte read from the cable by
the Z16C30 chip, will be automatically transferred to the SIO4’s onboard receive FIFO buffer. This
operation will continue as long as the receive FIFO buffer is not full.
4.5
INTERRUPTS
The SIO4 is capable of generating a number of interrupts to the host CPU, which may be utilized by the
application code or device driver to perform various operations. Interrupt sources may include, but are not
limited to, receive FIFO buffer almost empty, sync word detection, and Zilog Z16C30 serial controller chip
interrupts.
4.6
Upper/Lower Connector Naming Convention
Since all the cable transceivers are bidirectional, the serial Data and Clock signals can be transmitted or
received on two separate IO connector pins. The naming convention “Upper” and “Lower” is used in order
to differentiate between these two pins with identical function. Typically, one pin is used for receive data,
and the other pin is used for transmit. Separate controls for the transmitter/receiver enables allow the user
flexibility to monitor the transmit line or perform a standalone loop back test. This also allows two SIO4
boards to be connected directly or two channels to be connected directly using standard cabling options by
simply configuring the transmitter and receiver pins correctly.
Figure 5.4-2 shows the overall operation for the Upper/Lower Clock and Data signals. The clock enables are
controlled from the GSC Clock Control Register (Section 2.1.2) and the data signals are enabled in the GSC
Channel Control/Status Registers (starting at Section 2.1.5). Even though the clock and data lines have
separate enables, they will typically be set the same. For example, if you want to transmit on the Channel 1
Upper signals and receive on the Channel 1 Lower signals, the Upper Tx Clock and Upper Tx Data will be
enabled for transmit; and the Lower Rx Clock and Lower Rx Data should be enabled for receive.
